Samsung Electronics Co., Ltd.

Jeong-Kyu Ha

Jae-Min Jung

Sang-Uk Han

KwanJai Lee

KyongSoon Cho

Ji-yong Park

Kyong-Soon Cho

Soyoung Lim

Woonbae Kim

Na-rae Shin

So-Young Lim

Kwan-Jai Lee

Youngshin Kwon

Pa-Lan Lee

Kyoung-Suk Yang

Donghan Kim

Woon-bae Kim

Jung-woo Kim

JaeMin Jung

Kyoungsuk Yang

Sang-uk Han

Seung Hwan Kim

Jungwoo Kim

Inho Choi

Seung-Hwan Kim

Minki Kim

Min Ki Kim

Sungeun Jo

Yechung Chung

Young-Shin Kwon

Youngdoo Jung

Duckgyu Kim

PaLan Lee

Jikho Song

Young-shin Kwon

Duck Gyu Kim

Narae Shin

Kwan-jai Lee

A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Chip-on-film package having redistribution pattern between semiconductor chip and connection terminal

A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

Semiconductor device

Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

Semiconductor package

Disclosed are fingerprint sensor packages and display apparatuses including the same. The fingerprint sensor package comprises a flexible film having a top surface and a bottom surface opposite to the top surface, a fingerprint sensor surrounded by a cap, and a display driver integrated circuit on the flexible film. The fingerprint sensor and the display driver integrated circuit are mounted on the top surface of the flexible film.

Fingerprint sensor package and display apparatus including the same

A semiconductor package includes a substrate having a top surface on which a semiconductor chip is mounted and a bottom surface opposite the top surface, an upper metal pattern including an upper connection region to which an external electrical device is connected and a chip connection region to which the semiconductor chip is connected, a lower metal pattern including a lower connection region to which other external electrical device is connected, and an intermediate metal pattern electrically connecting the upper and lower metal patterns. The upper metal pattern provides at least three groups of inner leads. The lower metal pattern provides at least three groups of outer leads. A module, such as that of a display device, may include the semiconductor package.

Semiconductor package and semiconductor module including the same

In an embodiment, the film product includes a film substrate having a first surface and a second surface opposite the first surface. The film substrate has a length in a first direction and a width in a second direction perpendicular to the first direction. A first plurality of pads is on one of the first surface and the second surface, and the first plurality of pads is arranged in a third direction, the third direction being diagonal with respect to at least one of the first direction and the second direction. At least one merge line is electrically connecting at least two of the first plurality of pads.

Film product, film packages and package modules using the same

A sensing module substrate and a sensing module including the same are provided. The sensing module substrate includes a film substrate having a first surface and a second surface; sensing vias which penetrate the film substrate from the first surface to the second surface, each of the sensing vias being configured to be coupled to pixels of a semiconductor chip; and an interconnection pattern provided on at least one of the first surface and the second surface of the film substrate.

Sensing module substrate and sensing module including the same

Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.

Chip-on-film semiconductor packages and display apparatus including the same

A semiconductor package includes a flexible film substrate including a chip mounting region and a cut-line interposed between an inner region and an outer region of the flexible film substrate, the cut-line partially surrounding the inner region. The semiconductor package further includes first interconnection lines extending in the inner region from a first side of the chip mounting region towards an edge of the inner region of the flexible film substrate, and second interconnection lines extending in the outer region from a second side of the chip mounting region towards an edge of the outer region of the flexible film substrate. The edge of the inner region and the edge of the outer region are located on the first side of the semiconductor chip.

Semiconductor packages and package modules using the same

A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film.

Film for semiconductor package, semiconductor package using film and display device including the same

Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.

Chip-on-film package and device assembly including the same

A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Methods of fabricating tape film packages

Growing community of inventors

Hwaseong-si, South Korea

Jeong-Kyu Ha