Skhynix Inc.

Industry-University Cooperation Foundation Hanyang University

Jeong Kyoum Kim

Hyung Soo Kim

Jun Yong Song

Han Kyu Chi

Myeong Jae Park

Jae Duk Han

Eun Ji Song

Gi Jin Park

Disclosed is a continuous time linear equalizer circuit having a higher bandwidth by a plurality of filters connected to different signal paths in a T-coil circuit.

Continuous time linear equalizer

A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.

Semiconductor device

A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing shifted signals to the interference cancellation circuit.

Symbol interference cancellation circuit and system including the same

A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

Growing community of inventors

Icheon-si Gyeonggi-do, South Korea

Jeong Kyoum Kim