Skhynix Inc.

Other

Jeong Jun Lee

Choung Ki Song

Dae Suk Kim

Dong Kyun Kim

Mi Hyun Hwang

Soo Hwan Kim

Hoi Ju Chung

There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.

Method of performing a multiplication and accumulation (MAC) operation in a processing-in- memory (PIM) device

An operation method of memory may include activating a first row that is selected in a first bank, activating a second row that is selected in a second bank, receiving an all-bank counting command, reading a first access count from memory cells of specific columns of the first row in response to the all-bank counting command, increasing the first access count, writing the increased first access count in the memory cells of the specific columns of the first row, reading a second access count from memory cells of specific columns of the second row in response to the all-bank counting command, increasing the second access count, and writing the increased second access count in the memory cells of the specific columns of the second row.

Memory for performing counting operation, memory system, and operation method of memory

A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

Memory and operation method of memory

A Processing-In-Memory (PIM) device includes a first storage region and a multiplication/accumulation (MAC) calculator. The first storage region configured to store a first data. The MAC operator configured to execute a MAC calculation on the first data and second data in an MAC mode. When an error exists in the first data, the MAC operator compensates multiplication result data generated by a multiplying calculation of the first data and the second data and executes an adding calculation of the compensated multiplication result data.

Processing-in-memory (PIM) devices

A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Processing-in-memory (PIM) devices and methods of testing the PIM devices

An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

Apparatus for performing a repair operation

A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.

An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.

Electronic device for performing data masking operation

A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

Latch circuit and semiconductor memory device including the same

An electronic device includes an operation control circuit and an input data generation circuit. The operation control circuit generates a detection signal and an internal masking signal based on a masking signal and data during a write operation. The input data generation circuit converts input data based on the internal masking signal to generate converted data. In addition, the input data generation circuit selects and outputs either the converted data or drive data as the input data, which are input to a data storage circuit, based on the detection signal.

Electronic devices for executing a write operation

A semiconductor memory apparatus includes a first mat, a second mat, a column driver, and a connection circuit. The first mat may include a first mat column line. The second mat may include a second mat column line. The column driver may drive the first mat column line in response to a mat selection signal and a column decoding signal. The connection circuit may electrically couple or separate the second mat column line to or from the first mat column line in response to the mat select signal.

Semiconductor memory apparatus

A traffic information detection system and method. According to the traffic information detection method of the present invention, at least one loop coil on a road transmits a signal indicative of electric change induced in the loop coil by a vehicle, at least one loop detection device installed at the garden or escape zone of the road receives the signal transmitted from the loop coil and wirelessly transmits a signal indicative of whether or not a vehicle exists on a road, the velocity of and type of the vehicle, and a traffic signal controller wirelessly receives the signal transmitted from the loop detection device, thereby acquiring traffic information.

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Gwangju-si, South Korea

Jeong Jun Lee