Skhynix Inc.

Jeong Jin Hwang

Sung Nyou Yu

Duck Hwa Hong

Sang Ah Hyun

Soo Hwan Kim

Min Jun Choi

An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Memory device for performing smart refresh operation and method of reducing power consumption during refresh

A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Semiconductor device and semiconductor system

Memory device for performing smart refresh operation and memory system including the same

Growing community of inventors

Icheon-si Gyeonggi-do, South Korea

Jeong Jin Hwang