Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Jeong-Il Kim

Jong-Woong Chang

Hong-Woo Lee

Yun-Hee Kwak

Jong-Hyuk Lee

Sung-Man Kim

Jong-Hwan Lee

Yeong-Keun Kwon

Sang-Moon Moh

Hyeon-Hwan Kim

Yeon-Kyu Moon

Dong-Gyu Kim

Seung-Soo Baek

Bo-Ra Kim

Bon-Yong Koo

Back-Won Lee

Mi-Sun Lee

Sang-Jin Jeon

Jong Woong Chang

Kang Nam Kim

You Mee Hyun

Bae-Heuk Yim

Duc-han Cho

A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.

Gate driver and a display device including the same

A display device may include an insulating substrate, a pixel electrode formed on the insulating substrate, a circuit board connected to the insulating substrate, a first wiring connected to the circuit board, and a second wiring for transmitting a signal to the pixel electrode. The second wiring may be connected to the first wiring, and the second wiring may have a larger resistance than the first wiring. Portions of the first wiring or the second wiring may include a zigzag pattern, and a swing width of a zigzag pattern of the second wiring may be varied depending on the position of the second wiring.

Display device having fanout wiring

A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Method of driving a gate line and gate drive circuit for performing the method

The present invention relates to a thin film transistor array panel and a display device including the same. A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a plurality of gate lines; a plurality of pixels respectively connected to the gate lines; a gate driver comprising a plurality of stages connected to each other, the plurality of stages being respectively connected to the plurality of gate lines and applying gate signals to the plurality of gate lines; and a driver inspection unit separated from the gate driver and including at least three inspection stages, wherein each of the at least three inspection stages has a same structure as one of the plurality of stages of the gate driver.

Thin film transistor array panel having a driver inspection unit and display device including the same

A display apparatus includes a display panel including gate and data lines disposed thereon, and a plurality of driver integrated circuits ('ICs') on the display panel and electrically connected to data lines. Flexible printed circuit boards ('FPCBs') are disposed on the display panel and a printed circuit board to apply the control signal and the image signal from the printed circuit board to the driver ICs. There are less FPCBs than driver ICs. The driver ICs are divided into first and second driver groups; the data lines are divided into first and second groups of data lines. Driver ICs of the first driver group are directly connected to corresponding FPCBs, and driver ICs of the second driver group are connected to adjacent driver ICs. Each driver integrated circuit of the first driver group outputs a first repair signal to repair a data line of the first group of data lines.

Display apparatus and method of driving the same

A display substrate comprises a base substrate divided into a display region and a peripheral region surrounding the display region, wherein an image is displayed in the display region, a pixel part formed in the display region of the base substrate, a first color filter layer formed on the base substrate including the pixel part, wherein the first color filter layer is formed in the display region, and a second color filter layer formed in the peripheral region of the base substrate.

Display substrate comprising color filter layers formed in display and peripheral regions

A thin film transistor substrate includes a substrate, first and second pad sections, a signal wiring and a pixel array. The first pad section includes first and second lines. The first pad section receives a driving signal through at least one of the first and second lines. The second pad section includes a third line extending from the first line and a fourth line extending from the second line. The second pad section receives the driving signal through at least one of the third and fourth lines. The signal wiring in a display area is electrically connected to at least one of the third and fourth lines to receive the driving signal from the second pad section. The pixel array receives the driving signal from the signal wiring.

TFT substrate having first and second pad sections formed in peripheral area each with overlapping metal patterns receiving driving signals to repair electrically opened lines

A panel for a display device includes a shorting bar to dissipate an electrostatic charge and the first and second testing bars. Signal lines are divided into the first signal line group electrically connected to the first testing bar and the second signal line group electrically connected to the second testing bar. Floating transistors are formed between the shorting bar and the signal lines of the second signal line group.

Display device with floating transistor elements on alternating data lines

Growing community of inventors

Asan-si, South Korea

Jeong-Il Kim