Samsung Electronics Co., Ltd.

Jeong-hyuk Choi

Dong-Jun Kim

Kyung-joong Joo

Jong-han Kim

Jeong-Hyong Yi

Dong-jun Kim

Wang-chul Shin

Yong-ju Choi

Yun-Seung Shin

Myoung-Kwan Cho

Chan-Jo Lee

Jhang-rae Kim

Hun-kyu Lee

Jae-sun Yun

Keon-soo Kim

Jeong-hyong Yi

A method for programming a NAND-type flash memory device is provided. In the method for programming a NAND-type flash memory device having a plurality of strings two dimensionally arranged on the bulk area of a first conductivity type and a plurality of bitlines arranged in parallel on the plurality of strings, a bulk bias corresponding to a reverse bias is applied to the bulk area of the first conductivity type. At least one bitline is selected among the plurality of bitlines. At least one string is selected from among the plurality of strings connected to the selected bitline in parallel. At least one cell is programmed from among the plurality of cells within the selected strings.

Method for programming NAND-type flash memory device using bulk bias

A nonvolatile memory device having a lightly doped source and a method for manufacturing the same are provided. In the nonvolatile memory device, a first insulating layer, a floating gate, a second insulating layer and a control gate are sequentially formed on a semiconductor substrate, and a drain, a lightly doped source and a highly doped source are formed around a surface of the semiconductor substrate. At this time, the highly doped source is shallower than the drain without being overlapped by the floating gate. Thus, the integration of the memory cell can be increased, and the trapping of electrons is reduced in the first insulating layer formed between the floating gate and the lightly doped source, to thereby enhance the characteristics of the memory cell.

Nonvolatile memory device and method for manufacturing the same

A non-volatile memory device including a cell array region formed having a plurality of parallel bit lines, a plurality of parallel word lines, a plurality of memory cells, and a plurality of common source lines, the plurality of bit lines being orthogonal to the plurality of word lines, each of the memory cells being connected to a bit line and a word line and having a stacked gate comprised of a floating gate and a control gate and a source/drain region, the plurality of common source lines being parallel to the plurality of bit lines. The non-volatile memory device also includes a peripheral circuit region for driving the memory cells in the cell array region is formed. The cell array region includes one or more bulk bias contact structures for maintaining the voltage of a bulk region in which the cell array region is formed, at or below a predetermined voltage. The non-volatile memory device can uniformly maintain the voltage of a bulk region regardless of the position of memory cells without increasing the area of a cell array.

Nonvolatile memory device having bulk bias contact structure in cell array region

Flash type programmable nonvolatile memory unit cells are provided, along with a manufacturing method. Each unit cell is formed such that the interpoly dielectric layer and the control gate surround the top surface and also the four lateral surfaces of the floating gate. This increases the capacitance between the floating gate and the control gate, which improves a coupling ratio. This also improves electromagnetic shielding within each cell, which reduces cross talk between neighboring cells, and permits more dense integration.

Nonvolative semiconductor memory device with high impurity concentration under field oxide layer

A CMOS device which includes first and second wells formed in first and second regions of a semiconductor substrate, respectively, first and second transistors formed in the respective wells, a third transistor formed in a third region of the semiconductor substrate outside of the wells, a first impurity layer formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer deeper than the first impurity layer and formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without necessitating any additional, separate mask processing steps.

Method for manufacturing CMOS devices having transistors with mutually different punch-through voltage characteristics

A nonvolatile memory device having a predetermined threshold voltage is disclosed. In the nonvolatile memory device comprising a gate electrode including a control gate, a floating gate and a gate insulating layer, a source region and a drain region, a threshold voltage of an initial state applied to a word line such that the floating gate is electrically neutral is set to the mean value between the threshold voltage of a programmed state and the threshold voltage of an erased state. Thus, the amount of negative charges passing through a tunnel oxide layer during a program operation is the same as the amount of positive charges passing through the tunnel oxide layer during an erase operation, and an electric field formed on the tunnel oxide layer is minimized. Thus, the generation of electron traps in the tunnel oxide layer is reduced even though the program or erase operations are repeated, to thereby suppress the loss of the charges stored in the floating gate. As a result, the reliability of the device can be enhanced.

Nonviolatile memory device having improved threshold voltages in erasing and programming operations

A method for fabricating a flash memory device and a flash memory device fabricated by this method are provided. A device isolation film for defining an active region is formed over a predetermined region of a semiconductor substrate and a tunnel insulating film is formed over the surface of the active region. A plurality of floating gate patterns crossing the device isolation film and the active region are formed in parallel. Each of the plurality of floating gate patterns comprises a conductive layer pattern and a capping layer pattern, which are sequentially stacked. An impurity region of a different conductivity type from that of the semiconductor substrate is formed over the active region between the plurality of floating gate patterns. An insulating film pattern filling up a region between the plurality of floating gate patterns is formed. A floating gate and an isolated capping layer pattern are sequentially formed over the active region crossing each floating gate pattern by selectively etching a predetermined region of each floating gate pattern to expose the device isolation film crossing each floating gate pattern. The floating gate is then exposed by removing the isolated capping layer pattern. A plurality of word lines are formed over the exposed floating gate and the exposed device isolation film in a direction in which the plurality of word lines cross the device isolation film and the active region. Each of the plurality of word lines is insulated from the exposed floating gate by an inter-gate dielectric film.

Method for fabricating flash memory device and flash memory device fabricated thereby

A method for manufacturing a nonvolatile memory device is provided. After forming an etching damage prevention layer on the entire surface of a stacked gate structure and on the entire surface of a semiconductor substrate, a self-aligned source etching process is performed. Thus, damage to side walls of the stacked gate structure and an active region can be prevented during the self-aligned source etching process.

Method for manufacturing nonvolatile memory device capable of preventing damage to side walls of stacked gate and active region

A nonvolatile semiconductor memory device includes a p-type semiconductor substrate having a surface region, and bit lines formed as n-type first diffusion regions in the surface region, extending in a column direction. The bit lines define between them a plurality of separated, parallel channel regions, extending in a row direction. A plurality of conductive floating gates are formed over first portions of respective channel regions on a first insulating layer, and extend over portions of the first diffusion regions. A plurality of conductive control gates is formed to extend over the floating gates, and over second portions of the channel regions that are not covered by the floating gates. The control gates are separated from the floating gates and from the second portions by additional insulating layers. A common source line is formed by an elongated conductor extending in the column direction, over the control gates and insulated from them. A plurality of n-type second diffusion layers are formed in the surface region between successive second portions of the channel regions and connected to the common source line. These define an intermittent source line under the control gate layers. At the points of interruption, the second diffusion layers form selection transistors with the control gates, which are turned on or off depending on whether the corresponding cell is being read. When read, they prevent reading out any error data if the memory cell had been over-erased.

Flash-type nonvolatile semiconductor memory devices for preventing overerasure

Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios include the steps of forming a tunneling oxide layer on a face of a semiconductor substrate and then forming a forming a first conductive layer (e.g., doped polysilicon) on the tunneling oxide layer. A floating gate electrode mask is then patterned on the first conductive layer so as to expose a portion the first conductive layer. A second conductive layer is then patterned on the exposed portion of the first conductive layer and on sidewalls of the floating gate electrode mask, to define a concave or U-shaped floating gate electrode having conductive sidewall extensions. The sidewall extensions increase the effective area of the floating gate electrode and increase the capacitance coupling ratio which enables programming and erasing at reduced voltage levels. A first electrically insulating layer is then formed on the U-shaped floating gate electrode, opposite the tunneling oxide layer. A control gate is then formed on the first electrically insulating layer, opposite the U-shaped floating gate electrode.

Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios

An improved method for fabricating a NOR flash memory device having a cell array region and a periphery region near the cell array region is disclosed. The bit line contact regions of the cell array region are formed independently, using a different mask, from the word line contact regions of the cell array region, and the active contact region and the gate contact region of the periphery region, thereby allowing stable formation of all contact regions without etching damage. Also, plug ions are implanted into the bit line contact region of the cell array region, and a metal plug is formed in the bit line contact region and the word line contact region of the cell array region, and the active contact region and the gate contact region of the periphery region.

Method for manufacturing NOR-type flash memory device

There is provided a nonvolatile memory device and an operating method therof which can perform byte erasing and can be implemented high integration. The nonvolatile memory device has a plurality of cells, each including a stacked gate structure of a floating gate and a control gate. The cells are formed in an area where a plurality of bit lines arranged in parallel at specific intervals perpendicularly intersect a plurality of word lines arranged at specific intervals. The cells also include a plurality of source lines, each being arranged in parallel with the bit lines every byte, and a plurality of source select transistors formed in an area where the source lines intersect the word lines. Two cells are connected to a bit line via one bit line contact. Two cells symmetrically arranged with respect to each other and connected to the same bit line via respective bit line contacts share one active source region. The active source region is in parallel with the word line and is connected to the source line via the source select transistor and a source line contact, and the source line is electrically isolated from another source line.

Nonvolatile memory device and operating method thereof

An improved method of fabricating a flash memory cell is disclosed. A tunnel oxide film is formed on active regions. A first conductive film and a protective film are sequentially formed on the tunnel oxide film. The protective film on the isolation film is selectively etched, thus forming a protective film pattern on the tunnel oxide film. A sacrificial conductive film is formed on the resultant structure. The sacrificial conductive film and the first conductive film pattern are over-etched until the sidewalls and the upper surface of the protective film pattern are exposed, thereby exposing the center of the isolation film and simultaneously forming a first conductive film pattern having sloped sidewalls. With the present invention, an electrical field is prevented from being concentrated in an area between a control gate electrode and a floating gate because the floating gate have a sloped sidewall profile instead of sharp edges. Also, the recession of an isolation film between adjacent floating gates can be significantly avoided, consequently suppressing the deterioration of isolation between adjacent cells.

Method of fabricating cell of flash memory device

An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area. First channel stop impurity ions are implanted into the select transistor field area. A first field insulation layer is formed in the memory cell field area, and a second field insulation layer is formed in the select transistor field area, such that the first channel stop impurity ions lie beneath the second field insulation area. Second channel stop impurity ions are implanted through the central portion of the first field insulation area, such that the second channel stop impurity ions lie beneath the central portion of the first field insulation layer.

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Suwon, South Korea

Jeong-hyuk Choi