Samsung Electronics Co., Ltd.

International Business Machines Corporation

Jeong-Hoon Ahn

Kyoung-woo Lee

Kyung-Tae Lee

Yong-Jun Lee

Heon-jong Shin

Yoon-Hae Kim

Il-Goo Kim

Soo-Geun Lee

Jun-Jung Kim

Hyo-Seon Lee

Jin-Hyeung Park

Wan-Jae Park

Mu-Kyeng Jung

Hong-Jae Shin

Young-Bae Kim

Hyun-Min Choi

Sung-hoon Lee

In-hwan Kim

Soo-geun Lee

Hyeok-Sang Oh

Seung-man Choi

Sang-chul Lee

Hyo-Jong Lee

Bong-Seok Suh

Byung-jun Oh

Joon-Nyung Lee

Kyungtae Lee

Oluwafemi O Ogunsola

Yeon-Joo Kim

Chul-Yong Park

Kyoung-Pil Park

Suk-Hee Jang

Mu-Kyung Jung

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Wiring structures and semiconductor devices

Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors. Each of the decoupling capacitors may include a first capacitor metal wiring pattern connected to a high power supply line, a second capacitor metal wiring pattern spaced apart from the first capacitor metal wiring pattern and connected to a low power supply line, and a dielectric pattern between the first capacitor metal wiring pattern and the second capacitor metal wiring pattern.

Semiconductor devices including sealing regions and decoupling capacitor regions

In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.

Wiring structure and method of forming the same, and semiconductor device including the wiring structure

Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then 'cut' by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical 'open' (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.

Methods of testing integrated circuit devices using fuse elements

A semiconductor device having pads is provided. The semiconductor device includes first pads formed along a first row, and second pads formed along a second row. The first via contact portions extending from the first pads toward the second row, and second via contact portions extending from the second pads toward the first row. The first and second via contact portions are arranged along a third row between the first and second rows.

Semiconductor device having pads

Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Integrated circuit capacitor structure

In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Semiconductor device and method of manufacturing the same

Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

Scribe-line structures and methods of forming the same

Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern comprising at least two layers of different chemical compositions that includes at least an opening penetrating the intermetal dielectric film; forming a conductive film to fill the opening on the intermetal dielectric pattern; and etching the conductive film by means of a chemical/mechanical polishing operation until exposing an upper face of the intermetal dielectric pattern and the top of the filled opening so as to form a conductive pattern. An etching process is then performed to selectively remove an upper portion of the intermetal dielectric pattern. Because the intermetal dielectric film is variable in chemical composition according to different constituent layers, the upper portion of the intermetal dielectric pattern can be selectively removed by using a chemical etching composition that demonstrates etching selectivity relative to the different layers of the intermetal dielectric film.

Method for damascene process

Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Void-free metal interconnection structure and method of forming the same

Growing community of inventors

Yongin-si, South Korea

Jeong-Hoon Ahn