Sk Keyfoundry Inc.

Jeong Ho Sheen

Kang Sup Shin

Jong Yeul Jeong

Sang Geun Koo

Kyung Ho Lee

Guk Hyeon Yu

A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

Semiconductor device having high breakdown voltage capacitor

A method for manufacturing a semiconductor device is provided. The method includes providing a high-voltage isolation capacitor region and a mixed-signal integrated circuit region on a substrate, forming a bottom electrode on the high-voltage isolation capacitor region, forming a bottom metal line on the mixed-signal integrated circuit region, forming an inter-metal dielectric layer on the bottom electrode and the bottom metal line, forming a top via in the inter-metal dielectric layer, forming a low bandgap dielectric layer on the top via and the inter-metal dielectric layer, patterning the low bandgap dielectric layer to form a patterned low bandgap dielectric layer, depositing a thick metal film on the top via and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top metal line on the high-voltage isolation capacitor region and form a top electrode on the mixed-signal integrated circuit region.

Semiconductor device and semiconductor device manufacturing method with high-voltage isolation capacitor

A semiconductor device includes a substrate, the substrate includes a capacitor region and a metal wiring region. The capacitor region includes a lower electrode formed on the substrate, an interlayer insulating layer formed on the lower electrode, a dielectric layer pattern formed on the interlayer insulating layer, and an upper electrode formed on the dielectric layer pattern. The metal wiring region includes a lower metal wiring formed parallel to the lower electrode, the interlayer insulating layer formed on the lower metal wiring, an upper insulating layer formed on the interlayer insulating layer and having a thickness smaller than a thickness of the interlayer insulating layer, and an upper metal wiring formed on the upper insulating layer, and formed in parallel with the upper electrode. The upper insulating layer and the dielectric layer pattern are formed of different materials.

Growing community of inventors

Cheongju-si, South Korea

Jeong Ho Sheen