Samsung Electronics Co., Ltd.

Jeong-Hee Park

Yong-Ho Ha

Hideki Horii

Bong-jin Kuh

Soon-Oh Park

Horii Hideki

Jun-Soo Bae

Dong-Ho Ahn

Doo-Hwan Park

Zhe Wu

Jung-hwan Park

Jin-Woo Lee

Ji-Hye Yi

Sung-Lae Cho

Hyun-Suk Kwon

Ju-Chul Park

Hyun-Jo Kim

Byoung-Deog Choi

Hye-Young Park

Hyeong-Geun An

Joon-Sang Park

Tae-Wan Kim

Jong-Uk Kim

Young-Min Ko

Man-Sug Kang

Kyu-Mann Lee

I-Hun Song

Seol Young Choi

Myung-jin Kang

Seok-Jae Chung

Hee-Sook Park

Jang-Eun Lee

Jong-myeong Lee

Byoung-Jae Bae

Kwangmin Park

Gyu-Hwan Oh

Sung-Un Kwon

Dong-ho Ahn

Hyo-Jung Kim

Dong-Jun Seong

Jong-Chan Shin

Han-Bong Ko

Kwang-Min Park

Jin-ho Oh

Byong-Ju Kim

Young-Soo Lim

Byongju Kim

Myung-ho Kong

Han-young Kim

Jin-Ho Oh

Dong-jun Seong

Taek-jung Kim

Jun-Ku Ahn

Dong-Sung Choi

Keon-seok Seo

A variable resistance memory device may include a memory unit including a first electrode disposed on a substrate, a variable resistance pattern disposed on the first electrode and a second electrode disposed on the variable resistance pattern, a selection pattern disposed on the memory unit, and a capping structure covering a sidewall of the selection pattern. The capping structure may include a first capping pattern and a second capping pattern sequentially stacked on at least one sidewall of the selection pattern. The first capping pattern may be silicon pattern, and the second capping pattern may include a nitride.

Variable resistance memory device including silicon capping pattern

There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

Variable resistance memory devices

A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

Memory device

A variable resistance memory device includes a pattern of one or more first conductive lines, a pattern of one or more second conductive lines, and a memory structure between the first and second conductive lines. The pattern of first conductive lines extends in a first direction on a substrate, and the first conductive lines extend in a second direction crossing the first direction. The pattern of second conductive lines extends in the second direction on the first conductive lines, and the second conductive lines extend in the first direction. The memory structure vertically overlaps a first conductive line and a second conductive line. The memory structure includes an electrode structure, an insulation pattern on a central upper surface of the electrode structure, and a variable resistance pattern on an edge upper surface of the electrode structure. The variable resistance pattern at least partially covers a sidewall of the insulation pattern.

A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below,[GeSi(AsTe)][N]&#x2003;&#x2003;(1)

A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.

Method of fabricating semiconductor device

In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.

Method of manufacturing a phase change memory device

A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

Method of forming a phase change material layer pattern and method of manufacturing a phase change memory device

An example embodiment relates to a method including forming a bottom electrode and an insulating layer on a substrate, the insulating layer defining a first opening that exposes a portion of the bottom electrode. The method includes forming a variable resistance material pattern, including a plurality of elements, to fill the first opening. The variable resistance material pattern may be doped with a dopant that includes at least one of the plurality of elements in the variable resistance material pattern. The method includes forming a top electrode on the variable resistance material pattern.

Method of manufacturing variable resistance memory device

Provided are a phase change memory device and a fabricating method thereof. The phase change memory device includes a substrate, an interlayer dielectric layer formed on the substrate, first and second contact holes formed in the interlayer dielectric layer, and a memory cell formed in the first and second contact holes and including a diode, a first electrode on the diode, a phase change material layer on the first electrode, and a second electrode on the phase change material layer, wherein the first contact hole and the second contact hole are spaced apart from and separated from each other.

Phase change memory device, storage system having the same and fabricating method thereof

A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.

Method of forming resistance variable memory device

A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material.

Methods of forming a phase change layer and methods of fabricating a phase change memory device including the same

A method of fabricating a phase change memory having a unit memory cell is described. The unit memory cell includes a phase change element connected to a corresponding vertical cell diode. The phase change element is formed from a phase change material layer formed on an interlayer dielectric layer including a via hole, and etched using a plasma formed from a plasma gas having a molecular weight of 17 or less to form a respective phase change material pattern in the via hole.

Method fabricating phase-change semiconductor memory device

A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.

Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current

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Hwaseong-si, South Korea

Jeong-Hee Park