Samsung Electronics Co., Ltd.

University of California

Jeong-Hee Han

Chung-woo Kim

Ji-Young Kim

Kang L Wang

Augustin Jinwoo Hong

Yong-Jik Park

Sang-Jin Hyun

Sang-hun Jeon

Jae-woong Hyun

Hoon-Joo Na

Hyeok-Jun Son

Hyung-Seok Hong

Sang-Moo Choi

Byung-Gook Park

Sang-Bom Kang

June-Hee Lee

Wan-jun Park

Il-Han Park

Ju-Hyung Kim

Sung-ho Park

Sung-Ho Park

Yo-sep Min

Won-joo Kim

Jin-Seok Lee

Kyu-sik Kim

Soo-doo Chae

Sung-Wook Hwang

Sung-kyu Choi

Hye-Lan Lee

Jae-Yeol Song

Dong-hun Kang

Choong-Man Lee

Do-Haing Lee

Hee-soon Chae

Chan-Jin Park

Hyun-Sang Hwang

Hu-Yong Lee

Soo-Doo Chae

Youn-seok Jeong

Sung-Kee Han

Hong-Bae Park

Yung-hee Yvette Lee

Chan-jin Park

An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same

A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.

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A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Methods for manufacturing semiconductor devices using etch stop dielectric layers and related devices

Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.

Semiconductor device

A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

Method of fabricating semiconductor device using a work function control film

Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.

Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Methods of manufacturing non-volatile memory devices having insulating layers treated using neutral beam irradiation

A flash memory device can include a semiconductor fin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor fin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor fin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.

Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same

A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.

Multi-bit nonvolatile memory devices and methods of operating the same

A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Semiconductor device including high-k insulating layer and method of manufacturing the same

In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

Method of manufacturing a memory device having improved erasing characteristics

A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high &#x3ba; material.

Non-volatile semiconductor memory device with alternative metal gate material

A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.

Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices

Growing community of inventors

Hwaseong-si, South Korea

Jeong-Hee Han