Samsung Electronics Co., Ltd.

Jeon-Taek Im

Seong-Hyun Kim

Jong-Sang Choi

Zang-Hee Cho

Jong-Hoon Shin

Kyoung-Hun Kim

Yong-Joo Park

Sung-Jae Byun

Han-gu Sohn

Young-min Lee

Yun-Tae Lee

Woo-Suk Chung

Jin-hyoung Kwon

Gyoo-cheol Hwang

Sung-Bong Kang

Joong-Kyu Choi

Sung-Kook Bang

Kook-Hwan Kweon

Hee-Chail Park

A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.

NAND flash memory having C/A pin and flash memory system including the same

A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function.

Method of multi-interfacing between smart card and memory card, and multi-interface card

A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

Memory system and memory management method including the same

An optical disk drive includes a non-volatile memory. The optical disk drive is booted based on driving information stored in the non-volatile memory. When a write command is received from a host, the optical disk drive stores data to be recorded in an optical medium in the non-volatile memory and then writes the data in the optical medium independent of the host.

Optical disk drive including non-volatile memory and method of operating the same

A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch coupler, a first memory module, a memory controller configured to control the first memory module, and a printed circuit board on which the memory controller and the first and second sockets are installed and electrical signal lines are formed between the memory controller and the first and second sockets. The first memory includes a plurality of non-volatile memory devices and stores system software. The first memory module has a structure such that it can be installed at the first socket but cannot be installed at the second socket. The non-volatile memory system may further include a second memory module for an extension of the memory capacity. The second memory module has a structure such that it can be installed at the second socket but cannot be installed at the first socket. Accordingly, system failure caused by misusage of a non-volatile memory module can be prevented.

Non-volatile memory module for preventing system failure and system including the same

The present invention provides a system with a plurality of Bluetooth dongles connected to a single host. Each dongle is connected to a different port on the host and each dongle can accommodate a piconet of up to seven Bluetooth devices. The host communicates with the Bluetooth devices via Bluetooth channels. The host includes an application layer, a Host Control Interface (HCI) layer and an interface device driver layer. An Interface Map Table (IMT) is stored in the host. The IMT associates each port on the host with the BD address of a particular Bluetooth dongle and with the channels associated with the particular dongle. The HCI layer and the Interface handler layer consult the IMT to direct commands and data to the correct port on the host.

Enhanced bluetooth communication system

An apparatus and method for controlling a supply voltage of a multiple interface card includes a first voltage adjustment unit, a second voltage adjustment unit, an internal circuit, a first voltage controller, and a second voltage controller. The first voltage controller adjusts a first supply voltage to a first internal supply voltage used as an operating voltage of the internal circuit and supplies the first internal supply voltage to the internal circuit. The second voltage adjustment unit adjusts a second supply voltage to a second internal supply voltage used as an operating voltage of the internal circuit and supplies the second internal supply voltage to the internal circuit. The first voltage controller detects the first supply voltage and, according to the first supply voltage, either applies the first supply voltage to the first voltage adjustment unit or blocks the first supply voltage from the first voltage adjustment unit. The second voltage controller detects the second supply voltage and, according to the detected voltage, either applies the second supply voltage to the second voltage adjustment unit or blocks the second supply voltage from the second voltage adjustment unit.

Apparatus and method for controlling supply voltage in multiple interface card

A synchronous random access memory device having an external address mode of operation and a burst mode of operation, in which a counter control circuit resets a burst mode counter during the external address mode of operation.

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Anseong-si, South Korea

Jeon-Taek Im