Samsung Electronics Co., Ltd.

Jeon-Il Lee

Hyun-woo Kim

Jae-young Ahn

Cha-Won Koh

Dong-Chul Yoo

Hun-hyeong Lim

Young-jin Noh

Guk-Hyon Yon

Kwang-Min Park

Ju-Mi Yun

Joong-Yun Ra

Young-Seon Son

Jin Su Park

Do-Hyung Kim

Nae-in Lee

Ki-chul Kim

Sang-Hyun Lee

Young-Seok Kim

Young-wook Park

Han-jin Lim

Sang-Hoon Ahn

Jang-Hee Lee

In-Jae Lee

Jong-Min Baek

Seung-Min Lee

Hyun-jung Lee

Shin-Jae Kang

Young-kuk Kim

Sung-woo Kang

Woo-Kyung You

Young-Mook Oh

Dong-Hoon Han

Hong-Rae Kim

Won-Seok Yoo

Su-Min Kim

Hong-sik Shin

Jun-soo Lee

Sang-Ho Rha

Kaoru Yamamoto

Kee-Young Jun

Geun-O Jeong

Chae-mook Lim

Sung-Joo An

Hyo-Sung Lee

Sun-Soo Lee

Kevin Bae

Kyung-Wook Park

In a layer deposition method, a substrate is loaded into a process chamber. A gas filling tank is charged with a gas to a predetermined charge pressure. The pressure of the gas is elevated to a pressure greater than the predetermined charge pressure. The gas is introduced into the process chamber.

Layer deposition method and layer deposition apparatus

A semiconductor manufacturing apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is configured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.

Semiconductor manufacturing apparatus having an insulating plate

An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.

Etching method and methods of manufacturing semiconductor device using the same

Methods of forming patterns for semiconductor devices are provided. A method may include preparing a substrate including an etch target layer on a surface of the substrate; forming a mask pattern that includes a lower masking layer having a first density and an upper masking layer having a second density that is less than the first density, on the etch target layer; forming spacers that cover sidewalls of the lower masking layer and the upper masking layer; removing the mask pattern; and etching the etch target layer by using the spacers as an etching mask.

Methods of forming patterns with multiple layers for semiconductor devices

A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Semiconductor devices and methods of manufacturing the same

Non-volatile semiconductor devices

Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Methods of manufacturing semiconductor devices

A lithography apparatus and a method of using the same, the apparatus including a stage for accommodating a substrate that has a photoresist film thereon; a main unit on the stage, the main unit being configured to irradiate a projection beam to the photoresist film; and an electric field unit adjacent to the stage, the electric field unit being configured to apply an electric field to the photoresist film, wherein the electric field unit is configured to be turned on at a same time as or before irradiation of the projection beam, and is configured to be turned off at a same time as or after termination of the projection beam.

Lithography apparatus having effective thermal electron enhancement unit and method of forming pattern using the same

A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

Methods of forming wiring structures

Semiconductor devices and methods of fabricating the same are provided. The methods include preparing a template having a three dimensional (3D) stair type structure formed in intaglio, forming an imprint pattern having the stair type structure using the template, and simultaneously forming stair type patterns on a substrate using the imprint pattern.

Methods of fabricating semiconductor devices

Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.

Semiconductor devices having metal silicide layers and methods of manufacturing such semiconductor devices

Growing community of inventors

Suwon-si, South Korea

Jeon-Il Lee