Infineon Technologies Ag

Applied Materials, Inc.

Jens Schneider

Kai Esmark

Martin Wendel

Harald Gossner

Dieter Kaiser

Marcel Heller

Christian Cornelius Russ

Cornelius Christian Russ

Henning Feick

David Alvarez

Vlad Temchenko

Thomas Schulz

Klaus Roeschlau

Tarek Lutz

Kiran V Chatty

Gerardo Delgadino

Sebastian Schmidt

Krzysztof Domanski

Joerg Ortner

Ralf Rudolf

Felix Braun

Robert Gauthier

Andreas Greiner

Nicolo Morgana

Ying Xiao

Heiko Aßmann

Martin Blöcker

Gerd Ballhorn

Marcus Dankelmann

Chinteong Lim

Stefan Doering

Yves Fabien Rody

Karsten Friedrich

Angelika Jungmann

Udo Goetschkes

Guillaume Roesch

A method of implanting an implant species into a substrate at different depths is described. The method includes forming an implant mask over the substrate. The implant mask includes a first implant zone designed as an opening and a second implant zone designed as a block array. The implant species is implanted through the implant mask under an implant angle tilted against a block plane, such that a first implant area is formed by the implant species at a first depth in the substrate beneath the first implant zone and a second implant area is formed by the implant species at a second depth in the substrate beneath the second implant zone. The first depth is greater than the second depth.

Method of implanting an implant species into a substrate at different depths

The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

Avalanche diode having an enhanced defect concentration level and method of making the same

In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.

Method for producing a self-aligning masking layer

Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles.

Method for processing a carrier, a carrier, an electronic device and a lithographic mask

The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

Diode-based ESD concept for DEMOS protection

Embodiments of the invention describe a method for exposing an area on a substrate to a beam. The method includes adjusting a focus offset of the beam with respect to the area on the substrate, tilting the beam or tilting the substrate, and exposing the area on the substrate with the beam, thereby generating locations within the area exposed with different foci. Furthermore embodiments describe computer programs for controlling a photolithographic system to do the same and a photolithographic system for doing the same.

Method for exposing an area on a substrate to a beam and photolithographic system

In an embodiment, a method includes retrieving a layout of an integrated circuit design from a non-transitory computer readable medium, identifying a silicon controlled rectifier (SCR) structure in the layout, identifying a current injection site in the layout, and determining if a distance between the identified current injection site and the identified SCR structure is less than a first threshold. A violation is flagged if the determined distance is less than the first threshold.

System and method for detecting parasitic thyristors in an integrated circuit

A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production

Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region.

Semiconductor device with cooling element

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Munich, Germany

Jens Schneider