Nvidia Corporation

Nxp B.v.

Koninklijke Philips Corporation N.v.

Jens Roever

Robert Jan Schutten

Gerrit Ary Slavenburg

Tom J Verbeure

Timothy A Pontius

In various examples, a low-latency variable backlight liquid crystal display (LCD) system is disclosed. The LCD system may reduce latency and video lag by performing an analysis of peak pixel values within subsets of pixels using a rendering device, prior to transmitting the frame to a display device for display. As a result, the display device may receive the peak pixel value data prior to or concurrently with the frame data, and may begin updating the backlight settings of the display without having to wait for a substantial portion of the frame to be received. In this way, the LCD system may avoid the full frame delay of conventional systems, allowing the LCD system to more reliably support high-performance applications such as gaming.

Low latency variable backlight liquid crystal display system

A display controller generates a backlight illumination field (BLIF) based on a coarse point-spread function (PSF) and a correction PSF. The display controller samples the coarse PSF to accumulate light contributions from a larger neighborhood of LEDs around a given LCD pixel. The display controller samples the correction PSF to generate correction factors for a smaller neighborhood of LEDs around the given LCD pixel. The display controller interpolates samples drawn from the coarse PSF and samples drawn from the correction PSF and then combines the interpolated samples to generate a full resolution BLIF.

Parallel pipelines for computing backlight illumination fields in high dynamic range display devices

A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.

Low-latency high-dynamic range liquid-crystal display device

A display device includes a display controller that performs a high-throughput dithering operation. The display controller performs a quantization operation with pixel values generated by a graphics processor to generate quantized pixel values and residual error values. The display controller distributes the residual error values associated with a first group of quantized pixel values to a second group of quantized pixel values based on a set of distribution weights. A given distribution weight defines what fraction of a given residual error value is distributed to a given quantized pixel value included in the second group of quantized pixel values. The distribution weights are calibrated to permit the display controller to compute different fractions of residual error values using bit shifting logic instead of complex combinatorial logic.

Parallel implementation of a dithering algorithm for high data rate display devices

A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (P,C) that are otherwise configured to communicate over an address-based network (). Sync signals () are generated for each of producer and consumer circuits (P,C) from the address information encoded into requests that communicate the data streams output by the producer circuit (P) and expected by the consumer circuit (C). The sync signals () for the producer and consumer circuits (C) are then used to selectively modify the data stream output by the producer circuit (P) to a format expected by the consumer circuit (C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (C) expects more data than output by the producer circuit (P), and discarding data communicated by the producer circuit (P) when the consumer expects less data than that output by the producer circuit (P).

Self-synchronizing data streaming between address-based producer and consumer circuits

A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Two-phase data-transfer protocol

A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer. In this manner, dependent upon the degree of offset of the within-block sequence relative to the higher-level sequence, access to the buffer is often provided well before the entire block is provided to the buffer, thereby optimizing the speed at which the memory can be accessed.

Synchronization of non-sequential moving pointers

A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage pipelined network includes first and second stages, where the first stage is disposed intermediate the second stage and the shared resource. First and second arbitration circuits are coupled respectively to the first and second stages of the multi-stage pipelined network, with each arbitration circuit configured to receive requests for access to the resource from at least one initiator and forward such requests to the shared resource. The second arbitration circuit is configured to forward requests to the shared resource via the first arbitration circuit, and the first arbitration circuit is configured to communicate at least one arbitration signal to the second arbitration circuit for use by the second arbitration circuit in arbitrating between requests received thereby. The incorporation of deferred arbitration logic enables arbitration logic to span levels of hierarchy, thus enabling the logical design of the memory-access structure to be effectively decoupled from the physical design.

Hierarchical memory access via pipelining with deferred arbitration

The color-keyed regions of a color-keyed image are extracted from the color-keyed image, and the color-keyed regions and the non-color-keyed regions are independently scaled. The independently scaled regions are subsequently merged to form a scaled color-key image with clearly distinguished color-keyed regions and non-color-keyed regions. To minimize the blurring of edges in the non-color-key regions, the non-color-key colors are extended into color-keyed regions after the color-keyed information is extracted from the color-keyed image. To minimize the encroachment of the scaled color-keyed regions into the scaled non-color-keyed regions of the scaled color-key image, the edges of the scaled color-key regions are sharpened by defining the color-keyed region as the region wherein each scaled/filtered color-key value exceeds a non-zero threshold value. To facilitate the use of existing memory and structure in images that are encoded using three components per pixel, such as RGB, YUV, etc., the extracted color-keyed regions are stored in the memory structure that is typically used to store an optional fourth component, such as a transparency or texture parameter.

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Los Gatos, CA, United States of America

Jens Roever