Infineon Technologies Ag

Infineon Technologies Austria Ag

Jens Repp

Eric Pihet

Maximilian Mangst

Thorsten Hinderer

Magnus-Maria Hell

Tobias Islinger

A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.

Method and circuitry to apply an individual DC offset to electrodes on a large-scale ion trap quantum computer

A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.

Field bus driver circuit

In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

Bus transceiver

A circuit has a driver circuit with a slew-rate controller, an output stage and a monitoring circuit. The output stage is connected to a first bus line and to a second bus line, and the driver circuit is designed to control the output stage on the basis of a first logic signal in such a manner that a corresponding bus voltage is produced between the first bus line and the second bus line. The slew-rate controller is coupled to the driver circuit and is designed to set a slew rate of the driver circuit on the basis of an input signal. The monitoring circuit is designed to generate the input signal for the slew-rate controller, wherein the input signal indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal than during a data transmission phase of the data frame.

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Markt Schwaben, Germany

Jens Repp