Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technology Ag

Jens Peter Konrath

Hans-Joachim Schulze

Roland Rupp

Jochen Hilsenbeck

Stefan Krivec

Ralf Siemieniec

Wolfgang Bergner

Rudolf Elpelt

Christian Hecht

Dethard Peters

Caspar Leendertz

Romain Esteve

Ulrich Schmid

Ronny Kern

Bernd Zippelius

Anton Mauder

Wolfgang Werner

Thomas Basler

Andre Rainer Stegner

Andreas Voerckel

Michael Hell

Shiqin Niu

Paul Ellinghaus

Konrad Schraml

Laura Stoeber

Frank Dieter Pfirsch

Helmut Strack

Peter Irsigler

Ravi Keshav Joshi

David Laforet

Cedric Ouvrard

Stefan Woehlert

Stefan Kramp

Larissa Wehrhahn-Kilian

Reinhold Schoerner

Florian Grasse

Mihai Draghici

Hiroshi Narahashi

Andre Kabakow

Richard Gaisberger

Grzegorz Lupina

Ralf Otremba

Markus Zundel

Francisco Javier Santos Rodriguez

Werner Schustereder

Carsten Schaeffer

Thomas Krotscheck Ostermann

Juergen Steinbrenner

Oliver Hellmund

Olaf Storbeck

Daniel Kueck

Stefan Mieslinger

Knut Stahrenberg

Christian Stahlhut

Maik Langner

Thomas Ganner

Anatoly Sotnikov

Guenther Wellenzohn

Thomas Frank

Gregor Pobegen

Fabian Triendl

Georg Pfusterschmied

Paul Salmen

Tobias Schmidutz

Vice Sodan

Christian Westermeier

Boris Mayerhofer

Markus Neuber

A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

Silicon carbide device with a stripe-shaped trench gate structure

A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Zdefects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Zdefects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.

Semiconductor device having a silicon carbide drift zone over a silicon carbide field stop zone

A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

Method of producing a silicon carbide device with a trench gate

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

Semiconductor device with a passivation layer and method for producing thereof

A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

Semiconductor device and method for forming a semiconductor device

A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a first trench is formed in a silicon carbide layer. A second trench is formed in the silicon carbide layer to define a mesa in the silicon carbide layer between the first trench and the second trench. A first doped semiconductor material is formed in the first trench and a second doped semiconductor material is formed in the second trench. A third doped semiconductor material is formed over the mesa to define a heterojunction at an interface between the third doped semiconductor material and the mesa.

Semiconductor device

A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

Silicon carbide device with trench gate

A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.

Silicon carbide device with Schottky contact

An embodiment of a semiconductor device comprises a SiC semiconductor body, a gate dielectric and a gate electrode. A first trench extends from a first surface of the SiC semiconductor body into the SiC semiconductor body. A junction material is in the first trench, wherein the junction material and the SiC semiconductor body form a diode.

Semiconductor device including junction material in a trench and manufacturing method

A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.

Method of manufacturing a semiconductor device and semiconductor device

A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.

Semiconductor device including a passivation structure and manufacturing method

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.

Semiconductor device including silicon carbide body and method of manufacturing

A method for forming a semiconductor device includes forming a mask layer with a first implantation window on a semiconductor substrate and implanting dopants with a first implantation energy into the semiconductor substrate through the first implantation window to form a first portion of a doping region of the semiconductor device. The mask layer is adapted to form a second implantation window of the mask layer. Further, dopants are implanted with a second implantation energy into the semiconductor substrate through the second implantation window. The second implantation energy differs from the first implantation energy and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.

Semiconductor devices and methods for forming semiconductor devices

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Villach, Austria

Jens Peter Konrath