International Business Machines Corporation

Jens Noack

Holger Wetter

Joachim Keinert

Thomas Kalla

Monika Strohmer

Juergen Pille

Philipp Salz

Hans-Werner Anderson

Uwe Brandt

Markus Buehler

Katherine Eve

The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.

Layouting of interconnect lines in integrated circuits

In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

Activation of memory core circuits in an integrated circuit

A computer system may obtain a first schematic design netlist for a first IC design and a second schematic design netlist for a second IC design. The computer system may normalize the first netlist and the second netlist. The computer system may determine that the normalized first netlist is the same as the normalized second netlist. The computer system may obtain a first layout design data for the first IC design and a second layout design data for the second IC design. The computer system may determine that the first layout data is the same as the second layout data. The computer system may copy a sign-off data of the first IC design to the second IC design.

Enabling an incremental sign-off process using design data

Embodiments of the present invention provide systems and methods for reducing power consumption during the operation of a SRAM cell. Embodiments of the present invention reduce power consumption by determining switching activity, and based off a determination of low switching activity, gates off a core which is not written; and limits switching activity on the unaddressed core by applying the highest order bit.

NAND-based write driver for SRAM

An integrated circuit includes a static random access memory array. The static random access memory array includes at least two cores, wherein only one of the cores is written at a time. The integrated circuit further includes a tristate driver. The tristate driver is configured to apply a high impedance state to one of the cores that is not being written. A corresponding electronic dataset product includes a description for the integrated circuit expressed in a hardware description language. A corresponding computer-implemented method generates an electronic description for the integrated circuit expressed in a hardware description language.

Write-bitline control in multicore SRAM arrays

A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.

Growing community of inventors

Stuttgart, Germany

Jens Noack