Dialog Semiconductor (uk) Limited

Jens Masuch

Mark Johnathan Childs

Carsten Barth

Jindrich Svorc

Martin Faerber

Santosh Kulkarni

Giulio De Vita

Martin Farber

Rebecca Tristram

A single/Multi-phase PMIC built on silicon substrate with coil layers processed on top of the PMIC layers' is provided. The integrated coil is in a spiral form, with a gap at the center of the coil, making additional metal routing not required. The integrated coil has connection pads located in the center gap of the spiral form, limiting the overall inductor resistance to the device only. The on-die inductor may have a magnetic core wrapping the windings. The spiral form may be implemented in a circular design, or a racetrack (elongated spiral) design. The coil layers may be implemented as multiple coil layers or as a single coil layer, connected in parallel (with the same I/O pads), reducing the resistance and maintaining the inductance.

Integrated voltage regulator with integrated air-core inductor

A solution is provided for adaptive slope compensation in a DC-DC switching converter. Jitter is reduced for on times less than 50% Tpd by using two or more different slopes for the compensation ramp. Additionally, any discontinuities at the 50% duty cycle point are reduced. Details of the compensation ramp are described, where the ramp rate for the first half of the switching period, for on times greater than 50% Tpd, decreases with increasing on time until, at an on time of 100% Tpd, it is approximately zero. In addition, the ramp rate for the second half of the switching period, for on times greater than 50% Tpd, decreases with decreasing on time until, at a duty of 50%, it is equal to the ramp rate used for the first half of the switching period.

Adaptive slope compensation

A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.

Pulse width modulation circuit with reduced minimum on-time

The clock input of a buck converter is delayed, preventing sub-harmonic oscillation. The function may be achieved by implementing a clock delay generation circuit, configured to delay a next clock pulse by an amount of time directly proportional to the most recent on time of the high-side switch for peak-mode current control, inversely proportional to the most recent on time of the low-side switch for peak-mode current control, inversely proportional to the most recent on time of the high-side switch for valley-mode current control, or inversely proportional to the clock minus the most recent on time of the high-side switch for valley-mode current control.

Preventing sub-harmonic oscillation with clock delay compensation, in a DC-DC switching converter

The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.

A DC-DC current-control mode switching converter is disclosed, with peak-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a high side device when the coil current exceeds the variable current limit. The DC-DC switching converter includes a compensation ramp generator, configured to provide a compensation ramp signal, and an offset circuit, configured to provide an offset current. The DC-DC switching converter further includes an amplifier, configured to generate a control current proportional to the difference between an output voltage and a target voltage, and an adder, to combine the control current, the compensation ramp signal, and the offset current. A DC-DC current-control mode switching converter, with valley-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a low side device when the coil current falls below the variable current limit, is also disclosed.

Compensation ramp offset removal

A power converter comprises an inductor coupled between a switching terminal and an output terminal of the power converter, a high side switching element coupled between an input terminal of the power converter and the switching terminal, a low side switching element coupled between the switching terminal and a reference terminal, and a feedback circuit comprising a continuous comparator unit configured to compare a ramp signal with an error signal using a first enable signal, a latched comparator unit configured to compare the ramp signal with the error signal using a second enable signal, wherein the error signal is based on a difference between a reference voltage and an output voltage at the output terminal of the power converter.

Power converter

A multiphase power converter and a corresponding method is presented. The multiphase power converter contains a first and a second constituent switched-mode power converter. The first constituent switched-mode power converter provides, both in a first mode of operation and in a second mode of operation, a first phase current to an output of the converter. The second constituent switched-mode power converter provides, in the second mode, a second phase current to the output of the converter. The converter switches, depending on an operation condition of the converter, between the first mode and the second mode. A first transconductance of the first constituent switched-mode power converter is adapted when switching between the first mode and the second mode. By adapting the first transconductance, unsteadiness of the output voltage of the converter occurring during the switching between both modes of operation is minimized.

Multiphase power converter

A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.

Dynamic current limit circuit

An object of the disclosure is to provide a multiphase Buck, Boost, or other switching converter to give high efficiency over the full range of output currents, and to maximize the total output current the switching converter is able to supply, by fully utilizing every phase of the switching converter. Further, another object of this disclosure is to balance the asymmetric transconductance, such that the load share between phases is optimized for different load levels of coil value, coil type, pass-device scaling, and frequency. Still further, another object of this disclosure requires that each of the switching converter operates at a similar point of saturation current at each point along the output load range, and each phase provides a different percentage of the total output current.

Multiphase DCDC converter with asymmetric GM

A comparator circuit is described, which is configured to provide a control current and a control voltage based on a first input voltage and a second input voltage. The comparator circuit comprises an input amplifier configured to generate an output signal based on the first input voltage and the second input voltage, and offset means configured to generate a first offset. Furthermore, the comparator circuit comprises a first output circuit configured to generate the control current based on the output signal and based on the first offset. In addition, the comparator circuit comprises a second output circuit configured to generate the control voltage based on the output signal and not based on the first offset.

Dynamic current-limit circuit

In order to accelerate the response of buck converters to load transients buck converters having asymmetric phase designs having a load step detection are used. When a relatively large and fast load step is detected, the clock frequency of 'fast'valley mode phases is reduced, which are populated with fast, low value inductors. The clock frequency is returned to its normal rate when the current in the 'slow' phases has reached a suitable level.

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Munich, Germany

Jens Masuch