Infineon Technologies Ag

Other

Jens Luepke

Gunnar H Krause

Justus Kuhn

Michael Schittenhelm

Wolfgang Ernst

Jochen Mueller

Peter Poechmueller

Christian Stocken

Georg Erhard Eggers

Eric Cordes

Peter Poechmüller

A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Method and device for testing semiconductor memory devices

An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.

Address generator for generating addresses for testing a circuit

Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

Test data generator

A test circuit is adapted to test circuits having a high-frequency clock signal. The test circuit is positioned between a conventional tester and the circuit to be tested. The test circuit includes a frequency multiplication circuit which multiplies the clock signal of the conventional tester to produce a high-frequency clock signal. The test circuit also receives control signals from the conventional tester. The control signals are output to the circuit to be tested via a bus.

Test circuit

Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.

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Munich, Germany

Jens Luepke