International Business Machines Corporation

Jens Leenstra

Dieter F Wendel

Philipp Panitz

Markus Kaltenbach

Tobias Gemmeke

Juergen Pille

Maarten Jakob Boersma

Nicolas Maeding

Tim Niggemeier

Philipp Oehler

Hans-Werner Tast

Juergen Koehl

Hans Schlenker

Silvia Melitta Mueller

Vijayshankar Raman

Adam J Storm

Christopher Michael Abernathy

Rolf Sautter

Jochen Preiss

Christophe J Layer

Antje Mueller

Christoph W Wandel

Stefan Buettner

Christian Schweizer

Eduard Diner

Dung Q Nguyen

Claude Basso

Fabrice Jean Verplanken

Jean Louis Calvignac

Colin Beaton Verrilli

Harm Peter Hofstee

Hari Mony

Harry S Barowski

Chih-Jen Chang

William Elton Burky

Petra Leber

Kerstin Claudia Schelm

Wilhelm Ernst Haller

Holger Wetter

Wolfram M Sauer

Friedrich-Christian Wernicke

Peter Hofstee

Amaury Neve De Mevergnies

Markus Kaltenback

A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Instruction scheduling approach to improve processor performance

Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file.

Mechanism to speed-up multithreaded execution by register file write port reallocation

Various systems, apparatuses, processes, and/or products may be used to calculate an SHA-2 hash function in a general-purpose processor. In some implementations, a system, apparatus, process, and/or product may include the ability to calculate at least one SHA-2 sigma function by using an execution unit adapted for performing a processor instruction, the execution unit including an integrated circuit primarily designed for calculating the SHA-2 sigma function(s), and calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function(s). In certain implementations, the calculation of the SHA-2 sigma function(s) can be performed by the integrated circuit within a single instruction, allowing for a faster calculation of the SHA-2 hash function.

Apparatus and method for calculating an SHA-2 hash function in a general purpose processor

A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

Techniques for reusing components of a logical operations functional block as an error correction code correction unit

Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.

Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch.

Byte selection and steering logic for combined byte shift and byte permute vector unit

Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

An approach is provided in which a processor receives a scan request to scan data included in a data table. The processor selects a column in the data table corresponding to the scan request and retrieves column data entries from the selected column. In addition, the processor identifies the width of the selected column and selects a scan algorithm based upon the identified column width. In turn, the processor loads the column data entries into column data vectors and computes scan results from the column data vectors using the selected scan algorithm.

Fast predicate table scans using single instruction, multiple data architecture

A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.

Permute unit and method to operate a permute unit

A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system.

Method to reduce power consumption of a register file with multi SMT support

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Bondorf, Germany

Jens Leenstra