Infineon Technologies Ag

Siemens Aktiengesellschaft

Jens L&uuml;pke

Peter P&ouml;chm&uuml;ller

Justus Kuhn

Michael Schittenhelm

Jochen M&uuml;ller

Gunnar H Krause

Wolfgang Ernst

Dietrich Widmann

Frank Weber

Joseph Sillup

Hermann Haas

Peter Pochm&uuml;ller

Armin Wieder

The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

System for testing fast integrated digital circuits, in particular semiconductor memory modules

The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

System for testing fast synchronous semiconductor circuits

A component holder for testing electronic components having a carrier, at least one component socket arranged on the carrier and having a group of component contacts to accommodate and make contact with a component, and at least one group of adapter contacts, which are arranged in a predefined standard arrangement on the carrier and are connected to the component contacts.

Component holder for testing devices and component holder system microlithography

An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Field-effect-controlled transistor and method for fabricating the transistor

The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.

Method of testing a memory cell having a floating gate

The burn-in test device has a multiplicity of test receptacles (,. . . ) in a test board for receiving semiconductor memories. The test board is wired alternately in such a way that burn-in pulses can be applied to the semiconductor modules in dependence on its organization, with the result that the burn-in pulses are applied in each case to the total number of input/output lines.

Growing community of inventors

München, Germany

Jens Lüpke

Growing community of inventors

München, Germany

Jens L&uuml;pke

Jens Lüpke