Blackberry Corporation

Synaptics Corporation

Google Inc.

Epcos Pte Ltd

Sonion A/s

Epcos Ag

Sonion Nederland B.v.

Research in Motion Corporation

Jens Kristian Poulsen

Mohamad El-Hage

Yong Zhang

George Soliman Mankaruse

Per Magnus Fredrik Hansson

John Douglas McGinn

Lars Jørn Stenberg

Hari Hariharan

Perry Jarmuszewski

Aart Zeger Van Halteren

Trausti Thormundsson

Larry Edward Hawker

Lorenzo Crespi

Claus Erdmann Fürst

Henrik Thomsen

Nagula Tharma Sangary

Gino Rocca

Antanas Matthew Broga

Mark E Miller

Ali Abdollahzadeh Milani

Per Flemming Høvesten

Tomasz Hanzlik

George Shaker

Cyril Antoine Martin

Lars Stenberg

Carsten Fallesen

Paulus Spaanderman

Aswani Tadinada

Jozef Johannes Gerardus Bosch

Jozef J G Bosch

Mohammad Shajaan

Venkatasuryam Issa

Jacky Li

John Douglas Mcginn

Lars Jorn Stenberg

Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

Dynamic timing calibration systems and methods

Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.

Low power biquad systems and methods

Systems and methods for programmable pulse density modulation (PDM) components enable backwards compatibility while maintaining reasonable tolerances. A system includes a programmable PDM device, a PDM master device and a bus communicably coupling the programmable PDM device to the PDM receiver. The PDM device may include an audio sensor, audio input circuitry, a delta-sigma converter and a PDM transmitter and receiver. The PDM transmitter and receiver may send out PDM data from the PDM device and receive programming data from the PDM Master device. The PDM device may further include register space controlled by the PDM master device, a buffer storing audio data for wakeup word systems that store audio data when the PDM receiver is powered down, a bus holder to hold the previous value on the bus if no device is driving it, and/or a clock multiplier to multiply the incoming clock by a factor.

Pulse density modulation systems and methods

Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.

Phase-locked loop with dual input reference and dynamic bandwidth control

Systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with this bus. The inherent noise and jitter are utilized to increase the precision of the measurements thereby essentially using this uncertainty as a self-dithering for increased resolution in the measurements. During adaption, the delays may be adjusted in multiple step sizes for a faster adaption time.

Dynamic delay calibration of devices attached to bus systems utilizing time-multiplexed clock and data lines

Systems and methods for differential data transmission using an unterminated transmission line comprise a plurality of switches configured to control a differential voltage output on a pair of output lines, wherein the plurality of switches have a first state in which a high voltage is output on a first of the pair of output lines and a low voltage is output on a second of the pair of output lines, and wherein the plurality of switches have a second state in which the low voltage is output on the first of the pair of output lines and the high voltage is output on the second of the pair of output lines. A transition switch with an output impedance equal to that of the output lines will discharge the lines during a state transition so as to reduce to power consumption associated with changing states of the transmission line.

Low-power differential data transmission systems and methods

Data bus includes a device controller coupled to a first interface for digital communications using a first communications protocol, the device controller including a master bus controller controlling a multi-drop bus using a second communications protocol, and a slave device coupled to the multi-drop bus and configured to transmit and receive digital communications with the device controller using the second communications protocol. Each transmission line end is terminated using a device attached at one end of the transmission line and by another device attached at the other end. The second communications protocol supports multiple data rates using a fixed frame format. Safe synchronization may be established by systematically eliminating all false positions instead of searching for a valid candidate. Noise in the audio band may be lowered by scrambling of the data using a pseudo-random generator.

Low power, high bandwidth, low latency data bus

Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

Sample rate conversion circuit with noise shaping modulation

Systems and methods for low latency adaptive noise cancellation include an audio sensor to sense environmental noise and generate a noise signal, an audio processing path to receive an audio signal, process the audio signal through an interpolation filter, and generate a primary audio signal having a first sample frequency, an adaptive noise cancellation processor to receive the noise signal and generate an anti-noise signal, a direct interpolator to receive the anti-noise signal and generate an anti-noise signal having the first sample frequency, and a limiter to provide clipping to reduce a number of bits in the anti-noise signal, an adder operable to combine the primary audio signal and the anti-noise signal and generate a combined output signal, and a low latency filter to process the combined output signal.

Low delay decimator and interpolator filters

Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

Low power lattice wave filter systems and methods

Systems and methods for multichannel, multirate lattice wave filters receive digital signal channels at a first sample rate and include a first multiplexer to combine the digital signal channels into a first digital data stream, and a first lattice wave filter comprising a first delay elements and a first feedback path to the first multiplexer, the first lattice wave filter produces a first output digital data stream having a second sample rate that is different than the first sample rate. The first multiplexer is configured to receive a first feedback signal through the first feedback path and combine the first feedback signal with the digital signal channels to produce the first digital data stream. The system may include a first processing branch comprising the first multiplexer and the first lattice wave filter structure, and a second processing branch comprising a second multiplexer and a second lattice wave filter structure. This may enable the implementation of simplified filters of lower complexity by reuse of hardware.

Multichannel, multirate, lattice wave filter systems and methods

Data bus systems and methods include a device controller coupled to a first interface for digital audio data communications in accordance with a first communications protocol, the device controller including a master bus controller for controlling a multi-drop bus in accordance with a second communications protocol; and a first slave device coupled to the multi-drop bus and configured to transmit and receive digital audio data communications with the device controller in accordance with the second communications protocol. Each transmission line end is terminated using the device attached at one end of the transmission line and by another device attached at the other end and reflections due to mismatches in impedance by inclusion of intermediate signaling nodes are controlled to allow multi-drop device support and high speed signaling. The second communications protocol supports multiple audio data rates using a fixed frame format.

There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device.

Single wire bus system

Growing community of inventors

Kitchener, Canada

Jens Kristian Poulsen