Robert Boschgmbh

Infineon Technologies Ag

Jens Graf

Axel Aue

Jens Barrenscheen

Peter Rohm

Herman Roozenbeek

Martin Thomas

Hannes Estl

Angela Rohm, Legal Representative

Horst Wagner

Edwin Eberlein

Hans Partes

Manfred Kirschner

Hermann Roozenbeek

Jens Dr Barrenscheen

A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.

Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The first semiconductor chip transmits appropriate pilot data in order to prescribe to the second semiconductor chip what transmission rate is to be used by the second semiconductor chip to transmit the diagnostic data to the first semiconductor chip.

A memory arrangement is provided, which has a programmable memory and a first buffer memory associated with the programmable memory, to which buffer memory, in the case of a command access, at least one command following the accessed command is written. A second buffer memory may also be provided, to which buffer memory, in the case of a data access, at least one datum following the accessed datum is written. Also provided is a method for reading from a memory arrangement during program execution, wherein presence of a command access or a data access recognized, and a command following the accessed command is written to a first buffer memory and a datum following the accessed datum is written to a second buffer memory. Thus, in this manner, a separate buffer memory is described for data accesses, and thus the content of the buffer for command accesses is not overwritten or destroyed when data accesses occur during the program execution.

Memory arrangement and method for reading from a memory arrangement

A set of peripheral chips for realizing hardware functions of a control device has at least two electronic units, which allow partitioning for the purpose of providing at least one basic functionality for a control device. This first and/or second electronic unit(s) may typically be configured as application-specific electronic switching circuit (ASIC).

Set of peripheral chips

A memory element and a device having a processor and a memory element, the memory element being positioned outside of the processor and being connectible to a processor via address and/or data lines, the address and/or data lines are each configured in an LVDS structure having corresponding drivers and receivers, and the drivers and receivers each being integrated in the memory element or in the processor.

Device having a memory element, and a memory element

A method and device for controlling operational sequences, in particular in a vehicle, a functional unit being connected to a bus system, the functional unit and/or the bus system being monitored by a monitoring unit, and the monitoring unit disconnecting, by an access operation, the connection of the functional unit to the bus system in a reliability case, the monitoring unit's access or operation being configurable by the functional unit so that the access path of the monitoring unit is interruptable by a configuration apparatus, arrangement or structure.

Growing community of inventors

Gochsheim, Germany

Jens Graf