Intel Mobile Communications Gmbh

Infineon Technologies Ag

Intel Deutschland Gmbh

Infineon Technologies LLC

Jens Berkmann

Axel G Huebner

Xiao-an Wang

Thomas Herndl

Maria Fresia

Michael Lunglmayr

Burkhard Becker

Armin Haeutle

Mauro Bottero

Wolfgang Haas

Armin Häutle

Michael Janning

Bhawana Shakya

Gerald Hodits

Sasha Simeunovic

A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the received data. A decision metric representing a sum or a difference of the path metric and the correction term is computed. Based on the decision metric, it is decided on a detection of the control channel.

Method for control channel detection in wireless communications systems

A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.

Method and apparatus for turbo decoder memory collision resolution

A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.

Reduced contention storage for channel coding

A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments. The apparatus further includes a plurality of first CRC check units, wherein each of the first CRC check units is configured to perform a first CRC check of a respective one of the plurality of data segments, the plurality of first CRC checks being performed concurrently, and wherein each of the first CRC check units is configured to perform a second CRC check based on an output of the respective first CRC check unit.

Method and apparatus for performing a CRC check

An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

Iterative decoder

A device such as a worker, window-size and iteration control unit (WWICU) is proposed. The WWICU determines processing, iteration, and window information based on format information indicative of one or more formats to be processed by a decoding process. The processing information may include a number of parallel workers, the iteration information may include a number of half-iterations, and the window information may include a window size to be used in the decoding process. The WWICU then determines time information including a total cycle count based on the processing information, the iteration information, and the window information. In response to determining that the total cycle count is not beyond a threshold value, the WWICU may transmit configuration information including the processing, iteration, and window information to a device, such as a turbo decoding device, configurable to perform the decoding process based on the configuration information.

Worker and iteration control for parallel turbo decoder

A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments and a plurality of first CRC check units, wherein each of the first CRC units is configured to perform a CRC check of a respective one of the plurality of segments of data, and wherein the plurality of CRC checks are performed concurrently.

A method for detection of a control channel includes receiving data transmitted via the control channel. A control channel receive quality is estimated based on a metric difference between a metric of a known final trellis state and a minimum metric amongst the metrics of the trellis states based on the received data. It is decided whether or not to detect the control channel depending on the estimated control channel receive quality.

Control channel detection scheme

In a method of decoding data symbols into codewords, reliability information of the data symbols is provided. A first group of symbols from a first set of groups of symbols is selected, wherein the first set of groups of symbols is defined by at least a first parity-check of a parity-check matrix of a linear block code which has been used to encode the data symbols. The selection is based on the reliability information. A second group of symbols from a second set of groups of symbols is selected, wherein the second set of groups of symbols is defined by at least a second parity-check of the parity-check matrix. The selection is based on the selected first group of symbols and the reliability information. At least a part of the codeword is composed on the basis of the first group of symbols and the second group of symbols.

Decoder of error correction codes

A method for retransmission of erroneous data in a communications system includes receiving data blocks at a receiver that have been generated in a transmitter by the use of an error correcting code. The received data blocks are decoded by a linear programming algorithm. One or more symbols in the decoded data block are identified by subjecting the symbols in the decoded data block to an integrality criterion. A retransmission of a part of the data block based on the one or more identified symbols is then initiated.

Retransmission of erroneous data

In the method for termination of turbo decoding, a plurality of first LLR values (L(k)) of a-priori information and a plurality of second LLR values (L(k)) of extrinsic information are called up. A value is determined for a decision variable which is characteristic of the number of mathematical sign discrepancies between the first L(k)) and the second L(k)) values. The turbo decoding is terminated if the number of mathematical sign discrepancies is less than or at least equal to a first number or if the number is greater than or at least equal to a second number.

Method and apparatus for termination of iterative turbo decoding

Depending on the sequence of the decoded payload signal bits (a, . . . , a) and redundancy checking bits (p, . . . , p) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device () from the front into a linear feedback shift register (), or some of these bits are inserted by means of the distribution device () from the rear into a linear feedback shift register (), or all of them are inserted into a linear feedback shift register () from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register () without temporary storage of the bits produced by the decoding process.

Parallel processing for decoding and cyclic redundancy checking for the reception of mobile radio signals

A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.

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Munich, Germany

Jens Berkmann