Tsinghua University

National Taiwan University

Mediatek Corporation

Mfdiatek Inc.

Jenq-Kuen Lee

Yung-Chia Lin

Chung-Wen Huang

Jyh-Cheng Chen

Chung-Kai Chen

Ming-Yu Hung

Yi-Ping You

Shao-CHung Wang

Cheng-Yen Lin

Li-Chen Kan

Chung-Lin Tang

Cheng-Wei Chen

Wen-Li Shih

Yuan-Shin Hwang

Yi-Ping Yu

A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.

Probabilistic framework for compiler optimization with multithread power-gating controls

A method of allocating registers, includes for each of a plurality of live ranges of variables, calculating an energy saving value of each of the plurality of live ranges of the variables; classifying the plurality of live ranges of the variables into a plurality of queues according to the energy saving values of the plurality of live ranges of the variables; and assigning the plurality of live ranges of the variables in the plurality of queues into a plurality of registers.

Method and computing system of allocating registers

A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Task scheduling method for low power dissipation in a system chip

A method for scheduling instructions for clustered digital signal processors comprising a plurality of clusters, each cluster including at least two functional units and a first register file having a first unit, a second unit and a single set of access ports shared by the functional units comprises steps of checking whether executing one instruction needs data to be read from the first unit and the second unit of the first register file, generating a copying instruction to transfer data from the first unit to the second unit of the first register file, checking whether there is a prior operation cycle available to perform the copying instruction, scheduling the copying instruction in the prior operation cycle, and scheduling the instruction after the copying instruction.

Method for allocating registers using simulated annealing controlled instruction scheduling

A roaming method for maintaining connectivity between a client and a server through heterogeneous wireless networks includes the steps of establishing an initial connection between the client and the server through a first selected one of the heterogeneous wireless networks, detecting disconnection of the initial connection, and establishing a current connection between the client and server through a second selected one of the heterogeneous wireless networks upon detecting that the initial connection has been disconnected. A system, which includes the client and the server, for realizing the roaming method is also disclosed.

Roaming method for maintaining connectivity through heterogeneous wireless networks, and system for realizing the same

A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.

Processor employing a power managing mechanism and method of saving power for the same

Growing community of inventors

Hsinchu, Taiwan

Jenq-Kuen Lee