Infineon Technologies Ag

Other

International Business Machines Corporation

Infineon Technologies North America Corp.

Infineon Ag

Jenny Lian

Hua Shen

David Edward Kotecki

Haoren Zhuang

Ulrich Egger

Satish D Athavale

Rainer Bruchhaus

Gerhard Kunkel

Andreas Hilliger

Karl Hornik

Yun-Yu Wang

Nicolas Nagel

Martin Ostermayr

Sajan Marokkey

Chenting Lin

Klaus Herold

Stefan Gernhardt

Roberto Schiwon

Katherine Lynn Saenger

Laertis Economikos

Thomas J Shaw

Rajarao Jammy

Martin Gutsche

Robert B Laibowitz

John A Miller

Andreas Knorr

Horatio Seymour Wildman

Ronald J Schutz

Fen Fen Jamin

Uwe Wellhausen

Nirmal Chaudhary

Bum-Ki Moon

Keith K Wong

Nimal Chaudhary

Nicholas Nagel

Lee J Kimball

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Methods for forming contacts in semiconductor devices

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a method of manufacturing a semiconductor device includes a exposing a first photo resist layer using a first light beam thereby forming first features. The first exposure is performed by the first light beam passing through a first dipole illuminator and then a first mask. A dipole axis of the first dipole illuminator is oriented in a first direction. After exposing the first photo resist layer, forming second features using a second exposure with a second light beam. The second exposure is performed by the second light beam passing through a second dipole illuminator and then a second mask. A dipole axis of the second dipole illuminator is oriented in a second direction. The first direction and the second direction are not perpendicular. The first and the second features comprise a pattern for forming contact holes.

Gridded contacts in semiconductor devices

Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the AlOlayer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Method for forming ferrocapacitors and FeRAM devices

A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.

Device for inhibiting hydrogen damage in ferroelectric capacitor devices

A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.

Device and a method for forming a capacitor device

A ferroelectric capacitor device, such as an FeRAM device is formed of a substrate having one or more contact plugs extending therethrough, and a first interlayer dielectric layer formed on the substrate. A spacer layer is formed on the first interlayer dielectric layer, a first oxygen barrier layer is formed on the spacer layer and a buffer layer is formed on the first oxygen barrier layer. A layer of liner material is formed on the buffer layer between the buffer layer and the contact plugs and a dielectric layer is sandwiched between a first electrode and a second electrode. A second oxygen barrier layer is applied to the device. The spacer layer should prevent any oxidation from reaching the interface between the liner material and the contact plugs as this interface is located beneath the first oxygen barrier layer. As a result, the electrical contact is not damaged.

Ferroelectric capacitor devices and FeRAM devices

A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.

Method for producing a ferroelectric capacitor that includes etching with hardmasks

The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

Side-wall barrier structure and method of fabrication

A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroeletric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer, the conductive layer is patterned to form both the first and second electrodes.

Method of patterning capacitors and capacitors made thereby

A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

Method for forming an integrated barrier/plug for a stacked capacitor

In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode. A method of removing the hard mask material without damaging the surrounding surface includes the steps of: depositing a soft mask photoresist material over the composite surface, including the hard masked covered noble metal electrode and the dielectric surface, in a manner such that the soft mask material is thinner over the region of the noble metal electrode; removing the portion of the soft mask material over the noble metal electrode leaving the soft mask material over the dielectric surface; etching the hard mask material with the soft mask material protecting the dielectric surface; and removing the remaining portion of the soft mask material.

Method for removal of hard mask used to define noble metal electrode

A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.

Semiconductor structure and manufacturing method

A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.

Capacitor stack structure and method of fabricating description

A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.

Easy to remove hard mask layer for semiconductor device fabrication

A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.

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Wallkill, NY, United States of America

Jenny Lian