Xilinx, Inc.

Ventana Medical Systems, Inc.

Jennifer Wong

Alvin Y Ching

Bernard J New

James M Simkins

Stephen M Trimberger

Vasisht Mantra Vadi

John M Thendean

Steven P Young

Anna Wing Wah Wong

Richard A Carberry

Robert Anders Johnson

Raymond C Pang

David P Schultz

Christopher Bieniarz

Jerome W Kosmeder, Ii

Casey A Kernag

Walter N Sze

Ralph D Wittig

Peter H Alfke

Kameswara K Rao

Mark Lefever

Julia Ashworth-Sharpe

Scott O Frake

David B Squires

Jerome W Kosmeder

F Erich Goetting

Tony K Ngai

Venu M Kondapalli

Goran Hk Bilski

Jane W Sowards

Austin H Lesea

Schuyler E Shimanek

Thomas M Grogan

Richard C Li

Anthony L Hartman

Hassan K Bazargan

Goran Bilski

Scott S Nance

Eunice Y D Hao

Wayson J Lowe

Paula M Rodgers

Lidija Pestic-Dragovich

Catherine Wolf

Hiroaki Nitta

Mohammad R Tamjidi

Jacques Cavadenti

Angela Sattler

Thomas Grogan

A garment having an integrated breast pad holding apparatus used when lactating is disclosed. The garment includes a first fabric set sewn to a second fabric set to form a breast pad holder for a breast pad for each breast. The breast pad holder, one for each breast, is sewn to a fourth fabric having an elastic band. A wearable garment is attached to the fourth fabric at two or more sewn regions.

Garment with integrated breastfeeding pad holding apparatus

Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.

Antibody conjugates

Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.

Programmable device with dynamic DSP architecture

A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.

Digital signal processing element having an arithmetic logic unit

An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

Digital signal processing circuit having an adder circuit with carry-outs

A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

Digital signal processing block having a wide multiplexer

A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.

Digital signal processing circuit having a pattern circuit for determining termination conditions

A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Architectural floorplan for a digital signal processing circuit

An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Digital signal processing circuit having a SIMD circuit

An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.

Digital signal processing circuit having a pattern detector circuit for convergent rounding

An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Digital signal processing circuit having a pattern detector circuit

A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Digital signal processing circuit having a pre-adder circuit

An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.

Arithmetic logic unit circuit

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Fremont, CA, United States of America

Jennifer Wong