Xilinx, Inc.

Jennifer R Lilley

Glenn A Baxter

Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow.

Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed

A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Self aligning state machine

An architecture for a Block RAM (BRAM) based arbiter is provided to enable a programmable logic device (PLD) to efficiently form a memory controller, or other device requiring arbitration. The PLD arbiter provides low latency with a high clock frequency, even when implementing complex arbitration, by using BRAM to minimize PLD resources required. The architecture allows multiple complex arbitration algorithms to be used by allowing the multiple algorithms to be stored in BRAM. With multiple algorithms, dynamic configurability of the arbitration can be provided without halting the arbiter by simply changing an algorithm stored in BRAM. Additionally, algorithms can by dynamically modified by writing to the BRAM. With BRAM memory used for arbitration, PLD resources that would otherwise be wasted are frees up to be used by other components of the system.

Architecture for dynamically reprogrammable arbitration using memory

A data generator configured to provide a predictable data pattern, including system and product-by-process therefore, is described. The data generator is coupled to a circuit under test via a first data interface. The data generator is configured to generate a predictable data pattern for the circuit under test. The predictable data pattern is associated with display on a screen. A display controller is coupled to the circuit under test via a second data interface. At least one of a data monitor and a display device is coupled to the display controller.

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Mountain View, CA, United States of America

Jennifer R Lilley