International Business Machines Corporation

Jennifer Lane Vargus

Michael Stephen Floyd

Kevin Franklin Reick

Paul R Bastide

Larry Scott Leitner

Bradley David McCredie

Richard Tuthill Bassemir

Beth L Hoffman

Lakshminarayana Baba Arimilli

Joseph Allen Kirscht

Shiva R Dasari

Sudhir Dhawan

Carl J Anderson

Roger Ned Bailey

Hugh Rodney Stigdon

Barry Bradley Arndt

William M Buros

A crowd determined message response system may be provided. A message sent from a sender to at least one recipient over a communication network may be received. The message may be presented on a user interface device. A selection of a designated recipient for responding to the message may be received. A priority of the message sent to the designated recipient may be adjusted. The priority of the message sent to an unselected recipient of the message not selected as the designated recipient may be adjusted. The priority may be adjusted differently for the designated recipient and the unselected recipient. Based on the adjusting of the priority of the message sent to the unselected recipient, the order of importance in which the unselected recipient's messages are presented may be rearranged.

Crowd determined message response system

A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.

Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratio

A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of '1's. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of '1's in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of &#x201c;1&#x201d;s in their encoded rank select are initialized in parallel.

Memory initialization time reduction

The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.

Multi-state logic analyzer integral to a microprocessor

The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

Method and system for testing an integrated circuit

A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

Method and system for performing pseudo-random testing of an integrated circuit

Growing community of inventors

Cedar Park, TX, United States of America

Jennifer Lane Vargus