International Business Machines Corporation

Jennifer Kazda

Gi-Joon Nam

Gustavo Enrique Tellez

Yao-Wen Chang

Hua Xiang

Jinwook Jung

Chau-Chin Huang

Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program ('ILP') operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.

Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit

A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

White space insertion for enhanced routability

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Mohegan Lake, NY, United States of America

Jennifer Kazda