Advanced Micro Devices Corporation

Jennifer B Pencis

Atish Ghosh

Sanjiv K Lakhanpal

Chandrakant Pandya

Mark D Nicol

Warren G Stapleton

Mrityunjay R Hiremath

Keith R Shakel

Fred C Jair

A plurality of command segments comprising one command are received into an integrated circuit in a plurality of phases, each command segment being received in a different phase. The command segments are pushed into a command queue. Control logic checks for a cancellation indication for the command being received. If a cancellation indication is received, the control logic for the command queue performs an undo-push operation to remove the command segments stored in the command queue associated with the cancelled command.

FIFO with undo-push capability

A command filter selectively forwards received commands to a command queue for in-order execution. If the received command is a probe response command or if probe response information is extracted.from other commands, the probe response is stored in a storage location other than the command queue and executed out-of-order. Data movements specified by memory modifying commands already in the command queue and affecting the cache line in question are also performed out-of-order and the memory modifying command is discarded when it is removed in-order from the command queue.

Out-of-order probing in an in-order system

A development system includes two processors which can each act as the central processing unit of the development system. Control is passed between the processors via a system management mode (SMM) interrupt under the X86 architecture. In one embodiment, one of the processor is a processor to be emulated and the other processor is an emulating processor. Since the emulating processor runs at a much slower clock speed than the emulated processor, an application program can be run by the emulating processor until a region of interest is reached. The control of the application program can then be transferred by the SMM interrupt to the emulated processor. This arrangement allows a new compatible microprocessor to be efficiently developed using a hardware emulation system.

System and method for hardware emulation of a digital circuit

A primary cache test system is supplied using a secondary cache that closely matches specifications of the primary cache. Coherency is maintained between the primary and secondary caches using inclusion by a write-once protocol. The test system includes software which suspends cache operations on receipt of an error signal from a secondary cache controller or by periodically pausing cache operations for cache operation monitoring. During suspension of cache operations, the software verifies the states of the primary cache against the states and data within the secondary cache. Signals on cache hit and hit-modified pins that are available on the microprocessor integrated circuit are monitored to detect various error conditions. Error analysis includes detection of invalid hits to the primary cache, incorrectly modified lines in the primary cache and misses to the primary cache that should be hits.

On-chip primary cache testing circuit and test method

A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.

Two-stage memory refresh circuit

A conditional wait state generator is interposed into the timing circuitry of a processor. The conditional wait state generator provides for analysis of a selected cycle type and for selection of the latency or number of wait states that is imposed during processor execution for that selected cycle type. In accordance with another aspect of the conditional wait state generator, a method of analyzing processor performance under specific operating conditions involves selection of a particular cycle type for testing and selection of a number of wait states that is imposed on processor operations for the selected cycle type and not for other cycle types. A conditional wait state generator is interposed into the timing circuitry of a processor and thereby imposes the selected conditions on the processor for analysis.

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Austin, TX, United States of America

Jennifer B Pencis