International Business Machines Corporation

Jennifer A Navarro

Lisa Cranton Heller

Ute Gaertner

Frank Siegfried Lehnert

Chung-Lung K Shum

Markus Helms

Uwe Brandt

Rebecca S Wisniewski

Timothy John Slegel

Charles Franklin Webb

Michael F Fee

Barry Watson Krumm

Thomas G Koehler

Mark Anthony Check

Thomas Köhler

Christian Jacobi

Mark S Farrell

Pak-kin Mak

Aaron Tsai

John Stephen Liptay

Dean G Bair

Harald Boehm

Kattamuri Ekanadham

David Andrew Schroter

Il Park

Ka Shan Choy

A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Suspending translation look-aside buffer purge execution in a multi-processor environment

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Zone-SDID mapping scheme for TLB purges

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Quiesce handling in multithreaded environments

Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

Recovery improvement for quiesced systems

A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.

Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system

A facility is provided for processing to distinguish between a full conventional (or total system) quiesce request within a logically partitioned computer system, which requires all processors of the computer system to remain quiesced for the duration of the quiesce-related operation, and a new early-release conventional quiesce request, which is associated with fast-quiesce request utilization. In accordance with the facility, once all processors have quiesced responsive to a pending quiesce request sequence, the processors are allowed to block early-release conventional quiesce interrupts and to continue processing if there is no total system quiesce request in the pending quiesce request sequence.

Facilitating quiesce operations within a logically partitioned computer system

Storing translation lookaside buffer (TLB) entries are in a TLBat the processor. The TLBincludes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.

System, method and computer program product for providing a programmable quiesce filtering register

A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.

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Poughkeepsie, NY, United States of America

Jennifer A Navarro