Honeywell G.m.b.h.

Jennifer A Graves

Douglas A Fischer

Thomas D Snodgrass

Paul J Short

Thomas A Weingartner

Jordon W Woods

Paul E Knight

A parallel polygon/pixel rendering engine for a digital map capable of producing real-time linear shaded, three dimensional, raster graphics for video generation. The apparatus is suitable for use with avionic display systems, particularly digital map displays which include an instruction and interpreter unit and an image scanner. The apparatus comprises a raster engine, a memory interface and a bit mapped memory. The raster engine further includes a raster engine control and generic interpolation polygon processor interface, an edge interpolator, a line interpolator and a controller for the edge and line interpolators. The raster engine control is electrically connected to receive data from the instruction interface unit and is further electrically connected to the edge interpolator and interpolator controller. The edge interpolator is adapted to receive data from the raster engine control and the line interpolator is electrically connected to receive data from the edge interpolator. A first edge pipeline is connected to a second output of the raster engineer control and a second edge pipeline is connected to an output of the first edge pipeline as well as an output of the edge interpolator. An output from the second stage of the edge pipeline and a plurality of outputs from the line interpolators are then fed to a memory interface which is connected to receive data from the plurality of outputs. A bit mapped memory is also connected to receive data from the memory interface and control signals from a bit mapped memory controller. The bit map memory controller controls the memory interface components and the bit map memory during both normal and test modes.

Parallel polygon/pixel rendering engine

A display memory system consisting of a controller and a display memory that has a read display memory cycle time that is a non-integer multiple of the write display memory update rate. The display memory being partitioned into two frames of display memory with each frame having a plurality of subframes. The controller consisting of a read display memory decoder, a read display memory next subframe generator a read display memory latch and consisting of a write display memory decoder, a write display memory next subframe generator and write display memory latch.

Gerbil wheel memory

A memory interface controller apparatus for use in a digital system, such as a graphics display system. The apparatus comprises apparatus for receiving incoming pixel data and apparatus for detecting pixel address collision. In an alternate embodiment, apparatus for performing hidden surface removal on the incoming pixel data is included. The memory interface controller apparatus further may include apparatus for construction of images with transparent objects.

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Albuquerque, NM, United States of America

Jennifer A Graves