Intel Corporation

Jennefer S Hardin

Brian K Langendorf

Robert F Kubick

A computer system comprising a processor, a memory subsystem having a fast memory and a slow memory, and other at least one peripheral-performing variable length processor write cycles is described. The present invention includes a method and apparatus for generating signals to indicate write cycles to either a fast memory or a slow memory. The present invention also includes a method of generating signals to indicate the initiation of write cycle to a slow memory and avoiding the insertion of unnecessary wait states in write cycles to memory. The present invention further includes a method of minimizing wait states in a write cycle to memory. The computer system further includes a memory controller having a control flag signal to indicate a write to slow memory when asserted, and to indicate a write to a fast memory when deasserted. The control flag signal when asserted memory system includes a programmable address decoder having a writable memory which provides bank address signals.

Method and apparatus for performing variable length processor write

A computer system includes an apparatus for conserving power in a tag static random access memory (SRAM). The computer system includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The computer system also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags. The computer system includes a bus, a processor, a cache memory and a memory controller. The memory controller is comprised of a tag static random access memory (SRAM) which includes sense amplifier circuitry and control logic for activating the tag SRAM in response to an address strobe signal (ADS#) from the processor initiating access to the tag SRAM. The memory controller further includes control logic for keeping the tag SRAM activated during an access cycle and for deactivating the tag SRAM, including the sense amplifier circuitry, upon completion of an access cycle to the tag SRAM, thereby placing the tag SRAM in a reduced power consumption state.

Computer system including an apparatus for reducing power consumption in

A method and apparatus for conserving power in a tag SRAM. The present invention includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The present invention also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags.

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Orangevale, CA, United States of America

Jennefer S Hardin