Siliconsystems, Inc.

Jenn-Gang Chern

Rodney T Masumoto

Shunsaku Ueda

Tzu-Wang Pan

Kirby Lam

A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Method and apparatus for programmable damping factor of a phase locked

The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted. By utilizing a start-up sequence, the center frequency of the VCO is already settled when changing frequencies, the divide-by-M and divide-by-N counters are matched, the VCO starts in phase with the reference frequency of the reference signal, and the voltage of the loop filter is prevented from railing. By using dual buffered registers for each counter, loading of the divide-by-M and divide-by-N counters is accomplished without shutting down the VCO. A timer provides a 1.6 .mu.s delay to allow the DAC to settle. Digital logic is used to synchronize signals. Delay compensation circuitry is used to implement delay cancellation for zero phase restart.

Time based data separator zone change sequence

A one-shot control mechanism for ensuring close tracking of one-shot period to VCO period. The one-shot control mechanism provides immunity to data jitter and other spurious phenomena as well as stable and accurate tracking of one-shot period even when the VCO frequency varies from the center frequency of the VCO. The present invention includes a data capture PLL circuit and a frequency reference PLL circuit. The frequency reference PLL circuit provides a control signal to one or more one-shots to control their output pulse duration. Since the frequency reference PLL circuit operates at the expected frequency of data input, a relatively constant relationship may be maintained between the output pulse duration of the one-shots and the period of the VCO output.

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Yorba Linda, CA, United States of America

Jenn-Gang Chern