Nec Electronics Corporation

Jenn-Gang Chern

Shih-Ming Shih

Tzu-Wang Pan

Richard A Contreras

James Wilson Rae

Analog-to-digital converter (ADC) output bits are partitioned in a way that simplifies the phase error calculations. The circuit architecture embeds the implementation of the phase error calculations in the analog-to digital-converter (ADC) to simplify the overall circuit implementation. Simplification of the phase error calculations allows a reduction in the complexity of the circuits needed to implement the phase-locked-loop (PLL) for recovering the sampling clock.

Methods and structure for sampled-data timing recovery with reduced

Analog-to-digital (ADC) output bits are partitioned in a way that simplifies the gain error calculations. Simplification of the gain error calculations allows a reduction in the complexity of the circuits needed to implement automatic gain control (AGC).

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Sunnyvale, CA, United States of America

Jenn-Gang Chern