Sk Hynix Memory Solutions Inc.

Link a Media Devices Corporation

Skhynix Inc.

Lsi Corporation

Jenn-Gang Chern

Chun-Ju Shen

Mao-Ter Chen

Ye Liu

Danfeng Xu

Joseph Caroselli

Vishnu Balan

Yukeun Sim

Chintan M Desai

Huei-Ching You

Zichuan Cheng

The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.

Efficient digital duty cycle adjusters

An apparatus for temperature sensing may include: a bias generator suitable for generating a complementary-to-absolute-temperature (CTAT) bias voltage; a regulator suitable for regulating a bias voltage by using CTAT bias voltage and outputting a regulated bias voltage; and a ring oscillator suitable for receiving the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.

Temperature sensing apparatus

A voltage regulator, an active circuit, and a passive circuit is used. The active circuit is used to supply a reference signal as an input to the voltage regulator during a higher power mode. The passive circuit is used to supply a second reference signal as the input to the voltage regulator during a lower power mode, wherein the lower power mode consumes less power than the higher power mode.

Low power bias scheme for mobile storage SOC

A start-up circuit for a bandgap reference circuit include an operational amplifier and a diode coupled to a second input terminal of the operational amplifier. The circuit includes a first current branch including a first transistor and a second transistor in series, for generating a first current in response to an output voltage at an output terminal of the operational amplifier and a second current branch including a third transistor and a fourth transistor in series, for generating a second current in response to the output voltage. The circuit further includes a resistor coupled in parallel to the fourth transistor, an inverter coupled to a connection node between the third and fourth transistors, for inverting a voltage at the connection node and generating an inversion voltage, and a fifth transistor for controlling a switching element flowing a reference current proportional to the voltage with the negative temperature coefficient in response to the inversion voltage.

Start-up circuit for bandgap reference

A bias generator may include: an operational amplifier, a resister string, and a control circuit. The operational amplifier includes a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal. The resister string includes at least one resister coupled between a ground terminal and the output terminal of the operational amplifier, suitable for generating bias voltages. The control circuit is coupled between the second input terminal and the resister string, swaps the offset voltage, and selectively provides the offset voltage and the swapped offset voltage to the second input terminal of the operational amplifier.

Apparatus for correcting gain error of analog-to-digital converter

A calibration device for use in a memory system includes a bias circuit providing bias current, and a calibration unit generating a control signal for calibration. The bias circuit includes an internal resistor and measures a second bias current generated by mirroring a first bias current through the internal resistor, and adjusts the second bias current to generate the second bias current in a predetermined range as a third bias current. The calibration unit generates the control signal based on a comparison result between a reference voltage and a voltage generated based on the third bias current through an adjustable resistor.

Calibration device and memory system having the same

Apparatus for chip-to-chip communications may include a first driving unit and a second driving unit. The first driving unit may receive input data, generate a first output data based on the input data, and output the first output data. The second driving unit may receive the input data, generate a second output data with a pre-emphasis peak and output the second output data. The second output data may be generated by delaying and inverting the input data, and have a predetermined weight.

Driver structure for chip-to-chip communications

An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.

Delay locked loop (DLL) locked to a programmable phase

Offset is canceled by determining a voltage level to set a body input of a transistor to. The body input of the transistor is set to the determined voltage level to cancel offset associated with the transistor.

Offset cancellation by biasing the body of a transistor

An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Offset compensation scheme using a DAC

A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Growing community of inventors

Redwood City, CA, United States of America

Jenn-Gang Chern