Growing community of inventors

Portland, OR, United States of America

Jeng-Ya David Yeh

Average Co-Inventor Count = 5.33

ph-index = 6

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 103

Jeng-Ya David YehWalid M Hafez (28 patents)Jeng-Ya David YehChia-Hong Jan (28 patents)Jeng-Ya David YehJoodong Park (24 patents)Jeng-Ya David YehCurtis Tsai (22 patents)Jeng-Ya David YehGopinath Bhimarasetti (11 patents)Jeng-Ya David YehHsu-Yu Chang (4 patents)Jeng-Ya David YehNeville L Dias (4 patents)Jeng-Ya David YehChanaka D Munasinghe (4 patents)Jeng-Ya David YehPeter J Vandervoorn (2 patents)Jeng-Ya David YehRahul Ramaswamy (1 patent)Jeng-Ya David YehLuke J Mawst (1 patent)Jeng-Ya David YehNelson Tansu (1 patent)Jeng-Ya David YehJeng-Ya David Yeh (29 patents)Walid M HafezWalid M Hafez (169 patents)Chia-Hong JanChia-Hong Jan (147 patents)Joodong ParkJoodong Park (40 patents)Curtis TsaiCurtis Tsai (28 patents)Gopinath BhimarasettiGopinath Bhimarasetti (22 patents)Hsu-Yu ChangHsu-Yu Chang (31 patents)Neville L DiasNeville L Dias (17 patents)Chanaka D MunasingheChanaka D Munasinghe (14 patents)Peter J VandervoornPeter J Vandervoorn (4 patents)Rahul RamaswamyRahul Ramaswamy (45 patents)Luke J MawstLuke J Mawst (32 patents)Nelson TansuNelson Tansu (18 patents)
..
Inventor’s number of patents
..
Strength of working relationships

Company Filing History:

1. Intel Corporation (28 from 54,664 patents)

2. Wisconsin Alumni Research Foundation (1 from 4,119 patents)


29 patents:

1. 12136628 - High voltage three-dimensional devices having dielectric liners

2. 11881486 - High voltage three-dimensional devices having dielectric liners

3. 11695008 - Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process

4. 11610917 - High voltage three-dimensional devices having dielectric liners

5. 11251201 - High voltage three-dimensional devices having dielectric liners

6. 10854607 - Isolation well doping with solid-state diffusion sources for finFET architectures

7. 10847544 - High voltage three-dimensional devices having dielectric liners

8. 10692888 - High voltage three-dimensional devices having dielectric liners

9. 10658361 - Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process

10. 10643999 - Doping with solid-state diffusion sources for finFET architectures

11. 10340273 - Doping with solid-state diffusion sources for finFET architectures

12. 10263112 - Vertical non-planar semiconductor device for system-on-chip (SoC) applications

13. 10096599 - Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process

14. 10090304 - Isolation well doping with solid-state diffusion sources for FinFET architectures

15. 9972642 - High voltage three-dimensional devices having dielectric liners

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as of
12/4/2025
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