Etron Technology, Inc.

Exrontechnology, Inc.

Eton Technology, Inc.

Jeng-Tzong Shih

Tah-Kang Joseph Ting

Bor-Doou Rong

Chun Shiah

Ming Hung Wang

Shi-Huei Liu

Yung-Ching Hsieh

Ghy-Bin Wang

Po-Hung Chen

A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated.

Circuit architecture for effective compensating the time skew of circuit

A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Self-feedback control pipeline architecture for memory read path applications

A fuse circuit comprises at least one fuse circuit unit and a current blocking module. The fuse circuit unit comprises a voltage establishing module and a latch. The voltage establishing module is coupled to a first reference voltage source and includes a fuse that is capable of being selectively blown according to an initial setting signal. The fuse has a first terminal coupled to a node and a second terminal. The voltage establishing module establishes a voltage level on the node according to the blown-off status of the fuse. The latch is coupled to the voltage establishing module through the node for latching the voltage level of the node and generating the output signal. The current blocking module is coupled between a second reference voltage source and the second terminal of the fuse for blocking the current flowing through the fuse while initial setting.

Fuse circuit

A blocking section is inserted between the control section and the fuse section of a fuse control logic circuit. The blocking section comprises switching means which block the flow of DC current during a power-up sequence and thus avoids the collapse of the power supply voltage with the attending potential for incorrect addressing and improper function and timing options. The insertion of the blocking section further eliminates indeterminate logic states when fusible means are not fully blown thus assuring correct voltage levels at the output of the circuit.

Low power design for fuse control circuit

A memory device with burn-in capability is achieved. The device comprises, first, an array of memory cells, and, second, a burn-in test block. The burn-in test block comprises a memory address generator, a data pattern generator, and a command pattern generator. The burn-in test block is capable of writing data to the memory cells, of turning ON word lines in the array, and of holding the array in a static mode. A method to perform wafer level burn-in with this device is disclosed.

Wafer level burn-in for memory integrated circuit

A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells, wherein the dynamic memory cells require periodic refreshing, is achieved. The method comprises, first, determining if an external access to the dynamic memory array has been initiated. Second, a waiting period of RW idle time is inserted. The RW idle time comprises a sum of a row access time plus a pre-charge time. A pending refresh is performed during said RW idle time. A pending write access may be performed during the RW idle time. Finally, the external access is internally executed in the dynamic memory array after the RW idle time.

Delayed read/write scheme for SRAM interface compatible DRAM

A minimum pulse width detection and regeneration circuit is achieved. The circuit includes, first, a pulse width detector capable of detecting if an input signal pulse is within a range between a minimum width and a maximum width. Second, a pulse width extender is capable of extending the input signal pulse width to the maximum width if the input signal pulse is in the range. Finally, a glitch filter is capable of filtering out the input signal pulse if the input signal pulse is less than the minimum width.

Minimum pulse width detection and regeneration circuit

In this invention a global row redundancy scheme for a DRAM is described which effectively uses the resources of the chip to produce an area efficient design. The DRAM is constructed from two types of memory blocks, one that has a redundant cell array and one that does not. Both memory block types contain a memory cell array and bit line sense amplifiers. The bit line sense amplifiers, contained on the block with the redundant cell array, are shared with the memory cell array also contained in the block, and thus eliminating the need for sense amplifiers for use only with the redundant cell array. Although, every block could contain a redundant cell array, only one or two blocks with the redundant cell array are normally used. In the global row redundancy scheme repair can be made to any row containing a failed memory cell located in any memory block by using any unused rows in any redundant cell array, and in doing so provides a maximum effectiveness in repairing DRAM's that provides the opportunity to maximize yield.

Area efficient global row redundancy scheme for DRAM

Methods and circuits are disclosed for a semiconductor memory that allow one or more clock cycles per memory write operation, which allow the memory clock cycle time to be varied, and which minimize power dissipation. This is achieved by providing circuits that generate a minimum internal write time reference, independent of the chosen clock cycle time, so that a memory write cycle might take one clock cycle, or more than one clock cycle if the clock cycle is shortened.

Flexible time write operation

A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.

High speed programmable burst address generation circuit

A high speed clock-positive edge detection circuit with chip select control that produces a glitch-free transition detection pulse is described. The circuit comprises Logic, Conditioning and Output Sections. An n-channel transistor is connected between output C, output B and the Chip Select input. This eliminates glitches that would otherwise be present, as in the prior art.

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Hsinchu, Taiwan

Jeng-Tzong Shih