Taiwan Semiconductor Manufacturing Comp. Ltd.

Jeng-Shiun Ho

Hua-Tai Lin

Cheng-Cheng Kuo

Tzu-Chun Lo

Min-Hung Cheng

Ru-Gun Liu

Tsai-Sheng Gau

Kuei-Shun Chen

Chia-Chu Liu

Jye-Yen Cheng

Ken-Yu Chang

Chih-Hsiang Yao

Ching-Che Tsai

Luke Lo

Hsiao-Wei Su

Ming-Hsing Tsai

Wen-Chun Huang

Minghsing Tsai

Ming-Hui Chih

Chia-Ping Chiang

Yu-Po Tang

Cheng-Lung Tsai

Cheng-Kun Tsai

Shang-Yu Huang

Wei-Long Wang

Yu-Hsiang Lin

Bing-Syun Yeh

Cheng Cheng Kuo

Josh J H Feng

Ting-Chun Liu

Jing-Wei Shih

Wen-Han Chu

A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Method for removing semiconductor fins using alternating masks

Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Method for line stress reduction through dummy shoulder structures

The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.

Sub-resolution rod in the transition region

Dummy shoulder structure for line stress reduction

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Dissection splitting with optical proximity correction and mask rule check enforcement

Growing community of inventors

Hsin-Chu, Taiwan

Jeng-Shiun Ho