Nan Ya Technology Corporation

Delta Electronics, Inc.

Jeng-Ping Lin

Yi-Nan Chen

Ming-Cheng Chang

Pei-Ing Paul Lee

Ming Cheng Chang

Kuen-Chy Heo

Tieh-Chiang Wu

Chiang-Lin Shih

Hui-Min Mao

Chung-Yuan Lee

Chi-Hui Lin

Tseng-Fu Lu

Ching-Hsiung Tsai

Cheng-Chih Huang

Yinan Chen

Chih-Ching Lin

Neng-Tai Shih

Jer-Chyi Wang

Jih-Chang Lien

Tse-Yao Huang

Shing-Yih Shih

Shian-Jyh Lin

Chang-Rong Wu

Kuo-Chien Wu

Hsin-Jung Ho

Horng-Jou Wang

Hsu-Cheng Fan

Tie Jiang Wu

Jen-Jui Huang

Tie-Jiang Wu

Chih-Huang Wu

Chiang-Hung Lin

Chieh-Huang Lu

Chin-Piao Chang

Feng-Chuan Lin

Min-Ling Huang

Tse-Main Kuo

Hui-Chun Chu

Change-Rong Wu

Yu-Hua Chiao

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer.

Method for manufacturing semiconductor structure with buried power line and buried signal line

A controlling method of an encoder includes: detecting a rotation angle of a rotor of a motor coupled to the encoder to generate a first counting trigger signal and a second counting trigger signal so as to perform a turn number counting procedure; determining whether a period that an operating voltage of a driving circuit of the motor is smaller than a threshold voltage exceeds a preset time; and when the period exceeds the preset time, controlling a switching unit of the encoder to allow a battery of the encoder to provide a backup voltage to the encoder such that the encoder enters a low power processing procedure.

Encoder, motor and controlling method of encoder

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer.

Semiconductor structure with buried power line and buried signal line and method for manufacturing the same

An encoder includes a magnet, an optical coded disc, a magnetic sensing assembly, an optical sensing assembly and a signal processing unit. The optical coded disc has a first incremental pattern track and a second incremental pattern track. The magnet and the optical coded disc are structurally coaxial and rotatable. The magnet sensing assembly senses the magnet rotation to obtain an absolute position signal. The optical sensing assembly senses the optical coded disc rotation to obtain a first incremental position signal and a second incremental position signal. The signal processing unit receives and integrates those signals to obtain a high precision absolute position information.

Encoder using a magnetic sensing assembly and an optical sensing assembly and position detection method for a motor

An instant correction method for an encoder includes the following steps. The motion of a device under test is sensed to obtain a first wave signal and a second wave signal. The first and second wave signals are sampled to generate N first digital signal values and N second digital signal values. N positioning positions are generated according to the N first and second digital signal values, and the N positioning positions are added to a calculation group. A regression analysis is performed for the calculation group to generate a regression curve. The (N+1)-th prediction position is predicted using the regression curve. The ideal position of the device under test is determined at a time point of the (N+1)-th prediction position according to an ideal position curve. An error value between the (N+1)-th prediction position and the ideal position is applied to correct the device under test.

Instant correction method for encoder and system thereof

The present disclosure provide a method for preparing a semiconductor structure. The semiconductor structure includes a substrate having a memory array region and a peripheral circuit region; a plurality of first line patterns positioned in the memory array region and extending along a first direction; a plurality of second line patterns positioned over the first line patterns in the memory array region; and a plurality of linear features positioned in the peripheral circuit region. The plurality of second line patterns extend along a second direction different from the first direction. The plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.

Method for preparing a semiconductor structure having second line patterns and third line patterns formed over first line patterns

A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Method of manufacturing independent depth-controlled shallow trench isolation

A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Single-sided access device and fabrication method thereof

A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same

A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.

Memory device and fabrication method thereof

A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Fabrication method for a damascene bit line contact plug

A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

Semiconductor device having a trench gate and method of fabricating the same

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Taoyuan, Taiwan

Jeng-Ping Lin