Industrial Technology Research Institute

Tsinghua University

Jeng Kuen Lee

Yi-Ping You

Kuo Yu Chuang

Chung-Hsien Wu

Chi-Lung Wang

Chung Wen Huang

The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later.

Multi-thread power-gating control design

A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Power-gating instruction scheduling for power leakage reduction

Growing community of inventors

Tainan, Taiwan

Jeng Kuen Lee