Intel Corporation

Jeng-Jye Shaw

Gregory Scott Mathews

Dean A Mulla

John Wai Cheong Fu

Stuart E Sailer

A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

Processing ordered data requests to a memory

A technique for receiving a first data from a storage location in which the first data is not stored fully aligned within processor data boundaries for data retrieval. The adder also receives a second data having its alignment adjusted to correspond to the first data and adds the first data and the second data in CPU unaligned format. A carry control circuit coupled to the adder determines which carries are selected for transfer to the next stage for calculating a sum of the two data.

Unaligned semaphore adder

A memory with at least two banks, each bank capable of storing N=2.sup.n unique lines of data, each line of data addressable by an n-bit code corresponding to an address index i, 0.ltoreq.i.ltoreq.N-1, provides for operation in either an OR-line or split-line mode. In the OR-line mode, data from line i, corresponding to index i, is available from all banks. In the split-line mode, data is available from line address i of one set of banks, and address i+1 from another set of banks. In either mode, wrap-around from line address i=N-1 to i=0 is provided by the use of an additional line of memory located at a position corresponding to i=N that contains the same data as the line corresponding to i=0. In this manner, a complete wrap-around read capability is provided without suffering a memory speed loss.

Wrap-around mechanism for memory split-wordline read

A memory with at least two banks, each bank capable of storing N=2.sup.n unique lines of data, each lines of data addressable by an n-bit code corresponding to an address index i, 0.ltoreq.i.ltoreq.N-1, provides for operation in either an OR-line or split-line mode. In the OR-line mode, data from line i, corresponding to index i, is available from all banks. In the split-line mode, data is available from line address i of one set of banks, and address i+1 from another set of banks. In either mode, wrap-around from line address i=N-1 to i=0 is provided by the use of an additional line of memory located at a position corresponding to i=N that contains the same data as the line corresponding to i=0. In this manner, a complete wrap-around read capability is provided without suffering a memory speed loss.

Mechanism for performing wrap-around reads during split-wordline reads

A flip-flop circuit is described which comprises of a dynamic master which stores a signal by maintaining a charge representing the signal. It also comprises of a static slave which stores a signal by switching to a voltage potential representing the signal. A clock line is coupled to the master and the slave carrying a clock signal to control the master and the slave.

Dynamic-static master slave flip-flop circuit

An apparatus with improved response-time of a content addressable memory (CAM) directory table is obtained by replacing multi-stage domino TAG comparator and detection means with a single stage TAG comparator and detector for each TAG table entry. The improved response results from the use of a common ORed comparator output together with a small signal sense amplifier for the detection of the onset of a hit or miss. The single stage comparator and detector is suitable for use in cache memories including full associative, direct mapped, set associative and sector mapped caches.

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Palo Alto, CA, United States of America

Jeng-Jye Shaw