National Semiconductor Corporation

Integrated Device Technology, Inc.

Texas Instruments Corporation

Jeng-Jiun Yang

Constantin Bulucea

Sandeep Raj Bahl

William David French

Donald M Archer

D Courtney Parker

Peter B Johnson

Prasad Chaparala

Chuen-Der Lien

Fu-Chieh Hsu

Jeong Yeol Choi

David Courtney Parker

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors ('IGFETs'), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and) utilize empty wells (, and) in achieving desired transistor characteristics. Other IGFETs (, and) utilize filled wells (, and) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Configuration and fabrication of semiconductor structure using empty and filled wells

An asymmetric insulated-gate field-effect transistor (or) has a source (or) and a drain (or) laterally separated by a channel zone (or) of body material (or) of a semiconductor body. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A more heavily doped pocket portion (or) of the body material extends largely along only the source. The source has a main source portion (M orM) and a more lightly doped lateral source extension (E orE). The drain has a main portion (M orM) and a more lightly doped lateral drain extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions

An asymmetric insulated-gate field effect transistor (U orU) provided along an upper surface of a semiconductor body contains first and second source/drain zones (andorand) laterally separated by a channel zone (or) of the transistor's body material. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A pocket portion (or) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (---) at respective locations (PH--PH-) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone

Insulated-gate field-effect transistors ('IGFETs'), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (, or) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (, or). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (, or) has a main portion (M,M,M,M,M,M,M,M,M,M,M, orM) and a more lightly doped lateral extension (E,E,E,E,E,E,E,E,E,E,E, orE). Alternatively or additionally, a more heavily doped pocket portion (or) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.

Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket

A group of high-performance like-polarity insulated-gate field-effect transistors (, andor, and) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses

A semiconductor structure contains a bipolar transistor () and a spacing structure (-or-). The transistor has an emitter (), a base (), and a collector (). The base is formed with an intrinsic base portion (I), a base link portion (L), and a base contact portion (C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (-or-) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (-or-) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (-and-) laterally conform to opposite first and second lower edges (-and-) of the base link portion so as to determine, and thereby control, its length.

Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length

An asymmetric insulated-gate field effect transistor (U orU) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (andorand) laterally separated by a channel zone (or) of the transistor's body material. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A pocket portion (or) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH--PH--NH-) spaced apart from one another. This typically enables the transistor to have reduced current leakage.

Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone

A gate electrode () of a field-effect transistor () is defined above, and vertically separated by a gate dielectric layer () from, a channel-zone portion () of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion () using the gate electrode as a dopant-blocking shield. A spacer (T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (M andM) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (). Electrical contacts (and) are formed respectively to the source/drain portions.

Fabrication of asymmetric field-effect transistors using L-shaped spacers

A bipolar transistor (101) has a base (243) formed with an intrinsic base portion (2431), a base contact portion (245C), and a base link portion (243L) that extends between the intrinsic base portion and the base contact portion. An isolating dielectric layer (267-1 or 267-2) is provided above the base link portion. The length of the base link portion is determined, and thereby controlled, with a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, provided on the dielectric layer above the base link portion. The lateral spacing portion is typically provided as part of a layer of non-monocrystalline semiconductor material used in the gate electrode of an insulated-gate field-effect transistor.

An asymmetric insulated-gate field-effect transistor () has a source () and a drain () laterally separated by a channel zone () of body material () of a semiconductor body. A gate electrode () overlies a gate dielectric layer () above the channel zone. A more heavily doped pocket portion () of the body material extends largely along only the source. Each of the source and drain has a main portion (M orM) and a more lightly doped lateral extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions

A barrier layer impedes hydrogen diffusion into polysilicon resistors in circuits in which the resistor resistivity is sensitive to hydrogen diffusion into the resistors. The barrier layer extends laterally throughout the whole integrated circuit except for contact areas in which circuit elements overlying the barrier layer contact conductive elements underlying the barrier layer. The barrier layer includes a layer of polysilicon or amorphous silicon. In some embodiments, the barrier layer includes multiple layers of polysilicon or amorphous silicon that are separated by thin layers of silicon dioxide. In some embodiments, the barrier layer is formed between the polysilicon resistor and PECVD silicon nitride passivation which contains atomic hydrogen.

Integrated circuits that include a barrier layer reducing hydrogen

A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.

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Sunnyvale, CA, United States of America

Jeng-Jiun Yang