Industrial Technology Research Institute

Other

Jeng-Jie Peng

Ming-Dou Ker

Hsin-Chin Jiang

Chyh-Yih Chang

Tang-Kui Tseng

Nien-Ming Wang

The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

ESD protection design with turn-on restraining method and structures

An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

Electrostatic discharge protection device and method of manufacturing the same

An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

On-chip latch-up protection circuit

A method for improving the integrated circuits bonding firmness, whose principle is that after the later film is piled on top of the previous film, the upper surface of the later film will be affected by the previous film. Among the metal layers of the multi-level interconnection, the metal layer under and most close to the bond pad metal (the top metal layer of the multi-level interconnection) has a regular or an irregular layout pattern, which is under the predetermined regions serving as bond pad windows. These regular or irregular layout patterns result in a rough upper surface, and then improves the firmness of bond wires.

Method for improving integrated circuits bonding firmness

A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

Growing community of inventors

Tao-Yuan, Taiwan

Jeng-Jie Peng