Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Jeng-Hung Tsai

Ting-Hsu Chien

Chen-Yang Pan

Ming-Hsien Tsai

Wen-Juh Kang

Chih-Wen Cheng

A device for generating a duty cycle includes a converter, a corrector, and a control circuit. The converter is configured to generate a first output signal having a duty cycle to an output terminal according to an input signal. The corrector is coupled to the output terminal, and is configured to adjust the duty cycle of the first output signal according to a control signal. The converter is coupled in parallel with the corrector and between a first power source and a second power source. The control circuit is coupled to the output terminal, and is configured to generate the control signal according to the first output signal and a reference signal.

Device and method for generating duty cycle

A voltage mode transmitter is provided. The voltage mode transmitter includes a control unit and a resistor ladder circuit. The control unit receives a first signal and delays an inverse of the first signal for a time period to obtain a second signal. The resistor ladder circuit is configured to sum up products of the first signal or the second signal and a plurality of weights, thereby generating an output signal. The resistor ladder circuit includes an input terminal, multiple first resistors and a second resistor. The output terminal is configured to output the output signal. Each of the first resistors is coupled between the output terminal and the control unit and receives the first signal or the second signal. The resistances of the first resistors are 2R, 4R . . . and 2R respectively, where R is a reference resistance. The resistance of the second resistor is 2R.

Voltage mode transmitter

A clock and data recovery (CDR) circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on first and second clock signals received by the phase interpolator, so as to generate a phase interpolation signal. The finite state machine coupled to the phase detector and the phase interpolator generates the control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider coupled to the phase detector and the phase interpolator divides the second frequency of the phase interpolation signal by a divisor so as to generate the frequency dividing signal. A CDR method is also provided.

Clock and data recovery circuit and clock and data recovery method

An apparatus is provided. A first adder generates a first superposed signal in response to a first feedback equalization signal and an input signal. A second adder generates a second superposed signal in response to a second feedback equalization signal and the first superposed signal. An edge slicer generates an edge signal by slicing the first superposed signal. A data slicer generates a data signal by slicing the second superposed signal. An error slicer generates an error signal by slicing the second superposed signal. A CDR circuit generates a first and second clock signal in response to the data signal and the edge signal. An adaptive filter generates the reference signal and equalizer coefficients in response to data signal and the error signal. An equalizing unit generates the first feedback equalization signal and the second feedback equalization signal in response to the data signal and the equalizer coefficients.

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Santa Clara, CA, United States of America

Jeng-Hung Tsai