Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Jeng Gong

Wing-Chor Chan

Ying-Chieh Tsai

Wing Chor Chan

Tsung-Yi Huang

Shyi-Yuan Wu

Chih-Min Hu

Chien-Chih Chou

Ru-Yi Su

Chun-Lin Tsai

Puo-Yu Chiang

Chung Yu Hung

Li-Fan Chen

Chi-Hung Kao

Shih-Hui Chen

Chih Min Hu

Hsin Chia Chen

Tang-Jung Chiu

Kuo-Shu Huang

I-Lun Huang

Kuo-Hsu Huang

Meng-Chi Wu

Chia-Hui Cheng

Jia-Rong Yu

A high voltage (HV) device and method for manufacturing the same are provided, at least comprising a substrate, an insulation formed on the substrate, a deep well formed in the insulation, an air layer formed in the insulation and disposed adjacent to the bottom surface of the deep well. A bottom surface of the deep well is spaced apart from the substrate. Also, the air layer, interposed between the deep well and the substrate, is spaced apart from the substrate. In one embodiment, an air layer further communicates with an atmosphere outside the HV device, which facilitates heat dissipation.

High voltage device and method for manufacturing the same

A semiconductor device includes a substrate, a first doped well disposed in the substrate, a second doped well disposed in the substrate adjacent to a first side of the first doped well, a buffer region disposed in the first doped well adjacent to a second and opposite side of the first doped well, a gate structure disposed above the first side of the first doped well and extending along a first horizontal direction, a first contact region disposed in the buffer region toward the second side of the first doped well, a second contact region disposed in the buffer region adjacent to the first contact region, and a doped region disposed in the buffer region under the first contact region.

Semiconductor device

A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a first doping region, a first well and a second doping region formed in the substrate; a plurality of first heavily doped regions formed in the first doping region; a plurality of conductors and a plurality of dielectrics formed on the substrate between the first heavily doped regions; a second heavily doped region formed in the first well; a third heavily doped region and a fourth heavily doped region formed in the second doping region; as well as a first gate electrode and a first gate dielectric. The first doping region, the first well, the second heavily doped region and the fourth heavily doped region have a first type of doping. The second doping region, the first heavily doped regions and the third heavily doped region have a second type of doping.

Semiconductor structure having field plates over resurf regions in semiconductor substrate

A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.

Bipolar junction transistor and operating and manufacturing method for the same

Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region.

Semiconductor device and method of fabricating the same

A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.

Semiconductor device and operating method for the same

A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.

High voltage junction field effect transistor and manufacturing method thereof

A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.

Double diffused drain metal-oxide-semiconductor devices with floating poly thereon and methods of manufacturing the same

A semiconductor device and an operating method for the same are provided. The semiconductor device includes a first doped region, a second doped region, a first doped contact, a second doped contact, a first doped layer, a third doped contact and a first gate structure. The first doped contact and the second doped contact are on the first doped region. The first doped contact and the second doped contact has a first PN junction therebetween. The first doped layer is under the first or second doped contact. The first doped layer and the first or second doped contact has a second PN junction therebetween. The second PN junction is adjoined with the first PN junction.

A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.

JFET device and method of manufacturing the same

Double diffused drain metal-oxide-simiconductor devices with floating poly thereon and methods of manufacturing the same

A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification.

Multi-gate field-effect transistor with enhanced and adaptable low-frequency noise

A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between the second well region and the third well region over the fourth well region; and forming a patterned conductive layer including a pair of drain terminals on the pair of first doped regions, a pair of gate terminals on the pair of second doped regions, and a source terminal on the third doped region.

Junction-field-effect-transistor devices and methods of manufacturing the same

A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.

A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.

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Taichung, Taiwan

Jeng Gong