Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Industrial Technology Research Institute

Hiwin Mikrosystem Corporation

Jen-Yuan Chang

Chia-Ping Lai

Chien-Chang Lee

Tzu-Chung Tsai

Tsung-Shune Chin

Heng-Sheng Hsiao

Shih-Chang Chen

Jheng-Hong Jiang

Cheng-Kuo Sung

Chin-chou Liu

Sheng-Chih Wang

Long Song Lin

Hsien-Ting Chang

Sheng-Ching Wang

Yih Wang

Chia-En Huang

Yi-Ching Liu

Chi-Yuan Shih

Shih-Fen Huang

Hsiang-Fu Chen

Chia-Ming Hung

You-Ru Lin

Wei Ju Lee

Jwu-Sheng Hu

Jung-Hui Kao

Fu-Chiang Kuo

Cheng-Yi Lin

Ya-Hui Tsai

Chieh Lee

Mei-Hsuan Lin

Chen-Chung Du

Yi-Ping Huang

Yu-Ming Wang

Chi-Yuan Cheng

Kong-beng Thei

Shu-Wei Pu

Bor-Tung Jiang

Rong Syuan Fan

Tse-Pan Yang

Li-Wei Cheng

Brian Luan Chen

Sheng Kai Yeh

Kuo-Pei Lu

Wei-Chen Li

Chia-Hung Wu

Chun-Tse Lee

Zhi-Yong Chen

Chi-Ju Hsiao

A pick-and-place system is provided. The pick-and-place system includes: a wafer holder; a gantry over the wafer holder and comprising a stabilizer extending downwardly; a primary drive mechanism connected to the gantry and configured to drive the gantry; a secondary drive mechanism located at the gantry; and a suction head, wherein the secondary drive mechanism is connected to the suction head and configured to drive the suction head.

Pick-and-place system with a stabilizer

A semiconductor die assembly is provided. The semiconductor die assembly includes: a first bottom die and a second bottom die disposed at a bottom vertical level; a first top die disposed at a top vertical level above the bottom vertical level in a vertical direction and bonded to the first bottom die; a second top die disposed at the top vertical level and bonded to the second bottom die; and a linking die disposed at the top vertical level and bonded to both the first bottom die and the second bottom die. The linking die is characterized by a polygonal shape in a horizontal plane perpendicular to the vertical direction, and the polygonal shape is not a rectangle.

Semiconductor die assembly having a polygonal linking die

An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

Fan-out packages providing enhanced mechanical strength and methods for forming the same

A semiconductor structure comprises a semiconductor substrate, a first trench capacitor, and a second trench capacitor. The substrate has first trenches arranged in a first arrangement direction with each first trench extending in a first extension direction and second trenches arranged in a second arrangement direction with each second trench extending in a second extension direction. The first trench capacitor includes first capacitor segments disposed inside the first trenches. The second trench capacitor includes second capacitor segments disposed inside the second trenches. One first capacitor segment of the first capacitor segments has an extending length different from that of another first capacitor segment of the first capacitor segments, and one second capacitor segment of the second capacitor segments has an extending length different from that of another second capacitor segment of the second capacitor segments.

Package structure having trench capacitor

A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

Semiconductor die including guard ring structure and three-dimensional device structure including the same

A semiconductor device includes a substrate, a chip underlying the substrate, a chip overlying the substrate, and a dummy die overlying the substrate. A pattern of the dummy die includes a first interior sidewall and a second interior sidewall, and a stress relief material between the first interior sidewall and the second interior sidewall to form a dummy die stress balance pattern.

Semiconductor device and method of forming

A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.

Semiconductor device and method of manufacture

A method for placing a semiconductor onto a substrate is provided. The method includes the following steps: transferring, using a placement tool, the semiconductor along a path over onto the substrate; lowering, using the placement tool, the semiconductor to a predetermined height above the substrate; titling, using the placement tool, the semiconductor, to a predetermined angle; determining, using the placement tool, a first contact point of the semiconductor to the substrate at the predetermined angle; determining, using the placement tool, the first contact point is shift-off from an alignment position on the semiconductor with respect to the substrate; adjusting, using the placement tool, the first contact point to correct the shift-off; and lowering, using the placement tool, the semiconductor to make a first contact with the substrate at the corrected first contact point.

Semiconductor placing in packaging

An apparatus for manufacturing a bonded semiconductor structure includes a wafer processing unit including a first and second bonding chambers; a wafer transfer module including a first chamber coupled to the first and second bonding chambers, wherein the wafer transfer module is configured to transport a wafer within the first chamber and into and out of the wafer processing unit; a die transfer module including a second chamber coupled to the first and second bonding chambers, wherein the die transfer module is configured to transport a die carrier within the second chamber and into and out of the wafer processing unit; and a control system configured to control conditions of the first bonding chamber, the second bonding chamber, the first chamber and the second chamber. The first bonding chamber, the second bonding chamber, the first chamber and the second chamber are under same conditions controlled by the control system.

Apparatus for manufacturing a bonded semiconductor structure and method for manufacturing the same

A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

Semiconductor device including a plurality of dielectric materials between semiconductor dies and methods of forming the same

The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a metallic shield extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; and removing a portion of the redistribution layer to form a first opening over the photoelectric device. A metallic shield extending at least partially through the redistribution layer and surrounding the first opening is formed during the formation of the redistribution layer.

Semiconductor structure and method for forming the same

A semiconductor structure includes a first device structure, an oxide based layer, and a first auxiliary bond pad. The first device structure includes a first bonding layer. The oxide based layer is bonded to the first bonding layer of the first device structure. The first auxiliary bond pad is at an interface between the oxide based layer and the first bonding layer of the first device structure.

Semiconductor structure and method of manufacturing the same

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same

A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.

Three-dimensional integrated circuit

A device includes a substrate, at least one first dielectric layer on the substrate and including a first dielectric constant, at least one second dielectric layer on the at least one first dielectric layer and including a second dielectric constant greater than the first dielectric constant, and a dummy pattern including a first conductive pattern having a first pattern density in the at least one first dielectric layer and a second conductive pattern in the at least one second dielectric layer and comprising a second pattern density. The first pattern density is equal to or greater than the second pattern density.

Dummy pattern structure for reducing dishing

Growing community of inventors

Hsinchu, Taiwan

Jen-Yuan Chang