Other

Jen-Yen Wang

Chao-Yen Lin

Ming-Hong Fang

Guo-Jyun Chiou

Wen-Chou Tsai

Sheng-Hsiang Fu

Chih-Hao Chen

A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Growing community of inventors

Toufen, Taiwan

Jen-Yen Wang