Novatek Microelectronics Corp.

Jen-Ta Yang

Yen-Tao Liao

Min-Jung Chen

Yu-Hung Su

Hsin-Yi Chang

Huang-Chin Tang

Hung-Hsiang Chen

Heng-Yao Lin

Yung-Lung Chen

Rei-Hong Chang

Grace Li

Yun-Shu Yang

Yi-Wei Lin

Fu-Jung Wen

The disclosure provides a display driving device and a display control device and an operation method thereof. The display control device includes a data analyzing circuit and a data compensation circuit. The data analyzing circuit performs arithmetic operation on multiple sub-pixel data output by a target driving channel of a source driver in a current frame to obtain a resultant value corresponding to the target driving channel. The data compensation circuit determines at least one compensation grayscale value corresponding to the resultant value. The compensation grayscale value is to be displayed by the target driving channel in a vertical blank period of a frame period in which the current frame is displayed. The target driving channel of the source driver outputs at least one compensation voltage corresponding to the at least one compensation grayscale value in the vertical blank period of the frame period.

Display driving device and display control device and operation method thereof

A timing control device for the display panel includes a control circuit. The control circuit is configured to generate a plurality of gate scanning control signals and a data transmission control signal. In response to that a display refresh rate changes from a first frequency to a second frequency, the control circuit adjusts the plurality of gate scanning control signals to generate a plurality of adjusted gate scanning control signals, or adjusts the data transmission control signal to generate an adjusted data transmission control signal, for driving a display panel under the second frequency as the display refresh rate.

Timing control device and control method thereof

An image processing method with auto-adjusting gamma value is provided. This image processing method includes: receiving a detected value dependent upon a view angle between a normal direction of a screen and a sight direction of a viewer to the screen; receiving an original video frame with a plurality of pixels; determining at least one gamma table to obtain a gamma value for a pixel of the plurality of pixels according to the detected value, wherein there is an original pixel value corresponding to the pixel; and generating and outputting a corrected pixel value of the pixel based on the gamma value and the original pixel value of the pixel, wherein the screen is configured to show a corrected video frame having the pixel with the corrected pixel value. An image processing assembly and an image processing system are also provided.

Image processing method, assembly and system with auto-adjusting gamma value

The present invention discloses a driving method for a source driver, for driving a source line of a display panel. The driving method includes the steps of: driving the source line with a first voltage or a second voltage smaller than the first voltage in a first driving cycle; driving the source line with the first voltage in a second driving cycle next to the first driving cycle when the source line is driven with the first voltage in the first driving cycle; and driving the source line with an overdrive voltage in the second driving cycle when the source line is driven with the second voltage in the first driving cycle. The first voltage is a normal high voltage of the display panel, and the overdrive voltage is greater than the normal high voltage.

Driving method for source driver and related display system

A display device includes an image receiving unit, a power-saving control device, a display control unit, and a backlight module control unit. The power-saving control device judges whether or not received frames are still for a predetermined time. If the power-saving control device judges that the received frames are still for the predetermined time, the power-saving control device outputs a first control signal to the display control unit for controlling the display panel to perform power saving to reduce its power consumption while continuing displaying frames, and the backlight module control unit controls the backlight module to continue providing the backlight; while if the received frames are not still or are still for a time shorter than the predetermined time, the power-saving control device does not output the first control signal to the display control unit for controlling the display panel to perform power saving to reduce its power consumption.

Display device and display system with power-saving mechanism

A power-saving mechanism of display and a control method using the same are disclosed. The mechanism has no need as the prior art where a user's setting is needed to decide whether or not entering a power-saving operation mode or shutting off the display. The display power-saving mechanism of the present invention can judge whether or not the display frames are still; if the frames are still in a certain time, the display automatically enters the power-saving operation mode. The display power-saving mechanism is disposed in the hardware architecture of the display and capable of automatically judging whether or not to enter the power-saving operation mode without the user's setting.

Power-saving mechanism of display and control method using the same

Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.

Addressing method and structure for multiple chips and display system thereof

A system for parallel data transmission including a master device and a slave device is provided. The master device includes a first and a second I/O ports for outputting a read signal and a write signal, respectively. The slave device includes a third and a fourth I/O ports electrically coupled to the first and the second I/O ports, respectively. When the master device outputs the read or the write signal, the slave device transmits status information of the slave device to the master device after the master device has transmitted an address latch enable signal and before the slave device receives the address latch enable signal which is active. The master device outputs an address signal after transmitting the address latch enable signal and latches the address signal for the addressing for reading or writing data after the slave device has received the address latch enable signal.

Growing community of inventors

Hsinchu County, Taiwan

Jen-Ta Yang